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Message-Id: <20200826071407.10543-1-peng.fan@nxp.com>
Date: Wed, 26 Aug 2020 15:14:07 +0800
From: peng.fan@....com
To: sboyd@...nel.org, shawnguo@...nel.org, s.hauer@...gutronix.de
Cc: kernel@...gutronix.de, festevam@...il.com, linux-imx@....com,
abel.vesa@....com, Anson.Huang@....com, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Peng Fan <peng.fan@....com>
Subject: [PATCH] clk: imx: fix composite peripheral flags
From: Peng Fan <peng.fan@....com>
According to RM, for peripheral clock slice,
"IP clock slices must be stopped to change the clock source.".
So we must have CLK_SET_PARENT_GATE flag to avoid glitch.
Signed-off-by: Peng Fan <peng.fan@....com>
---
drivers/clk/imx/clk-composite-8m.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 78fb7e52a42a..2c309e3dc8e3 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -216,6 +216,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
div->width = PCG_PREDIV_WIDTH;
divider_ops = &imx8m_clk_composite_divider_ops;
mux_ops = &clk_mux_ops;
+ flags |= CLK_SET_PARENT_GATE;
}
div->lock = &imx_ccm_lock;
--
2.28.0
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