linux-kernel - Re: [PATCH v6 27/76] x86/sev-es: Add CPUID handling to #VC handler

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Date:   Thu, 27 Aug 2020 18:48:10 -0400
From:   Arvind Sankar <nivedita@...m.mit.edu>
To:     Joerg Roedel <joro@...tes.org>
Cc:     x86@...nel.org, Joerg Roedel <jroedel@...e.de>,
        Tom Lendacky <thomas.lendacky@....com>, hpa@...or.com,
        Andy Lutomirski <luto@...nel.org>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Jiri Slaby <jslaby@...e.cz>,
        Dan Williams <dan.j.williams@...el.com>,
        Juergen Gross <jgross@...e.com>,
        Kees Cook <keescook@...omium.org>,
        David Rientjes <rientjes@...gle.com>,
        Cfir Cohen <cfir@...gle.com>,
        Erdem Aktas <erdemaktas@...gle.com>,
        Masami Hiramatsu <mhiramat@...nel.org>,
        Mike Stunes <mstunes@...are.com>,
        Sean Christopherson <sean.j.christopherson@...el.com>,
        Martin Radev <martin.b.radev@...il.com>,
        linux-kernel@...r.kernel.org, kvm@...r.kernel.org,
        virtualization@...ts.linux-foundation.org
Subject: Re: [PATCH v6 27/76] x86/sev-es: Add CPUID handling to #VC handler

On Mon, Aug 24, 2020 at 10:54:22AM +0200, Joerg Roedel wrote:
> From: Tom Lendacky <thomas.lendacky@....com>
> 
> Handle #VC exceptions caused by CPUID instructions. These happen in
> early boot code when the KASLR code checks for RDTSC.
> 
> Signed-off-by: Tom Lendacky <thomas.lendacky@....com>
> [ jroedel@...e.de: Adapt to #VC handling framework ]
> Co-developed-by: Joerg Roedel <jroedel@...e.de>
> Signed-off-by: Joerg Roedel <jroedel@...e.de>
> Link: https://lore.kernel.org/r/20200724160336.5435-27-joro@8bytes.org
> ---
> +
> +static enum es_result vc_handle_cpuid(struct ghcb *ghcb,
> +				      struct es_em_ctxt *ctxt)
> +{
> +	struct pt_regs *regs = ctxt->regs;
> +	u32 cr4 = native_read_cr4();
> +	enum es_result ret;
> +
> +	ghcb_set_rax(ghcb, regs->ax);
> +	ghcb_set_rcx(ghcb, regs->cx);
> +
> +	if (cr4 & X86_CR4_OSXSAVE)

Will this ever happen? trampoline_32bit_src will clear CR4 except for
PAE and possibly LA57, no?

> +		/* Safe to read xcr0 */
> +		ghcb_set_xcr0(ghcb, xgetbv(XCR_XFEATURE_ENABLED_MASK));
> +	else
> +		/* xgetbv will cause #GP - use reset value for xcr0 */
> +		ghcb_set_xcr0(ghcb, 1);
> +
> +	ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_CPUID, 0, 0);
> +	if (ret != ES_OK)
> +		return ret;
> +
> +	if (!(ghcb_rax_is_valid(ghcb) &&
> +	      ghcb_rbx_is_valid(ghcb) &&
> +	      ghcb_rcx_is_valid(ghcb) &&
> +	      ghcb_rdx_is_valid(ghcb)))
> +		return ES_VMM_ERROR;
> +
> +	regs->ax = ghcb->save.rax;
> +	regs->bx = ghcb->save.rbx;
> +	regs->cx = ghcb->save.rcx;
> +	regs->dx = ghcb->save.rdx;
> +
> +	return ES_OK;
> +}
> -- 
> 2.28.0
>