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Message-ID: <CAPBb6MWZRKpg-rs7X_j3tqqsYHy=NkEMN1NdZwPS9zo-0whTJw@mail.gmail.com>
Date: Thu, 27 Aug 2020 19:10:13 +0900
From: Alexandre Courbot <acourbot@...omium.org>
To: Matthias Brugger <matthias.bgg@...il.com>
Cc: Tiffany Lin <tiffany.lin@...iatek.com>,
Andrew-CT Chen <andrew-ct.chen@...iatek.com>,
Hans Verkuil <hverkuil-cisco@...all.nl>,
Yunfei Dong <yunfei.dong@...iatek.com>,
Maoguang Meng <maoguang.meng@...iatek.com>,
Linux Media Mailing List <linux-media@...r.kernel.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>,
devicetree <devicetree@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 09/17] arm64: dts: mt8183: add encoder node
On Thu, Aug 27, 2020 at 7:03 PM Matthias Brugger <matthias.bgg@...il.com> wrote:
>
>
>
> On 21/08/2020 12:36, Alexandre Courbot wrote:
> > Now that the MT8183 encoder driver is ready, add its DT node. Also pull
> > the iommu and scp ones, which the encoder depends upon.
>
> Please don't do that. Instead of pulling in other DT nodes, it would be handy to
> get a reference of the series this is based on.
>
> Let me try to hunt them down now :)
Sorry, I'm not sure to understand - do you mean each node should come
with its own patch? Or that all the code should be merged before
sending these nodes? The rest of this series should land into the
media tree soon, if you prefer I can resend this patch separately once
that happens.
>
> Regards,
> Matthias
>
> >
> > Signed-off-by: Alexandre Courbot <acourbot@...omium.org>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 10 ++++++
> > .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 12 +++++++
> > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 36 +++++++++++++++++++
> > 3 files changed, 58 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > index ae405bd8f06b..9e77b420eee8 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> > @@ -25,6 +25,16 @@ memory@...00000 {
> > chosen {
> > stdout-path = "serial0:921600n8";
> > };
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > + scp_mem_reserved: scp_mem_region {
> > + compatible = "shared-dma-pool";
> > + reg = <0 0x50000000 0 0x2900000>;
> > + no-map;
> > + };
> > + };
> > };
> >
> > &auxadc {
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > index f0a070535b34..3c763be658da 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> > @@ -90,6 +90,18 @@ pp3300_alw: regulator6 {
> > regulator-max-microvolt = <3300000>;
> > };
> >
> > + reserved_memory: reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + scp_mem_reserved: scp_mem_region {
> > + compatible = "shared-dma-pool";
> > + reg = <0 0x50000000 0 0x2900000>;
> > + no-map;
> > + };
> > + };
> > +
> > max98357a: codec0 {
> > compatible = "maxim,max98357a";
> > sdmode-gpios = <&pio 175 0>;
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > index 102105871db2..8f77eea6df27 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > @@ -8,6 +8,7 @@
> > #include <dt-bindings/clock/mt8183-clk.h>
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > #include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/memory/mt8183-larb-port.h>
> > #include <dt-bindings/reset-controller/mt8183-resets.h>
> > #include <dt-bindings/phy/phy.h>
> > #include "mt8183-pinfunc.h"
> > @@ -339,6 +340,25 @@ pwrap: pwrap@...0d000 {
> > clock-names = "spi", "wrap";
> > };
> >
> > + iommu: iommu@...05000 {
> > + compatible = "mediatek,mt8183-m4u";
> > + reg = <0 0x10205000 0 0x1000>;
> > + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
> > + #iommu-cells = <1>;
> > + };
> > +
> > + scp: scp@...00000 {
> > + compatible = "mediatek,mt8183-scp";
> > + reg = <0 0x10500000 0 0x80000>,
> > + <0 0x105c0000 0 0x19080>;
> > + reg-names = "sram", "cfg";
> > + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&infracfg CLK_INFRA_SCPSYS>;
> > + clock-names = "main";
> > + memory-region = <&scp_mem_reserved>;
> > + status = "disabled";
> > + };
> > +
> > systimer: timer@...17000 {
> > compatible = "mediatek,mt8183-timer",
> > "mediatek,mt6765-timer";
> > @@ -772,6 +792,22 @@ vencsys: syscon@...00000 {
> > #clock-cells = <1>;
> > };
> >
> > + vcodec_enc: vcodec@...20000 {
> > + compatible = "mediatek,mt8183-vcodec-enc";
> > + reg = <0 0x17020000 0 0x1000>;
> > + interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_LOW>;
> > + iommus = <&iommu M4U_PORT_VENC_REC>,
> > + <&iommu M4U_PORT_VENC_BSDMA>,
> > + <&iommu M4U_PORT_VENC_RD_COMV>,
> > + <&iommu M4U_PORT_VENC_CUR_LUMA>,
> > + <&iommu M4U_PORT_VENC_CUR_CHROMA>,
> > + <&iommu M4U_PORT_VENC_REF_LUMA>,
> > + <&iommu M4U_PORT_VENC_REF_CHROMA>;
> > + mediatek,scp = <&scp>;
> > + clocks = <&vencsys CLK_VENC_VENC>;
> > + clock-names = "MT_CG_VENC";
> > + };
> > +
> > ipu_conn: syscon@...00000 {
> > compatible = "mediatek,mt8183-ipu_conn", "syscon";
> > reg = <0 0x19000000 0 0x1000>;
> >
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