linux-kernel - Re: [PATCH RFC 1/2] riscv/kvm: Fix use VSIP_VALID

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Message-ID: <CAAhSdy2+auxYci5guLqtbEf3bO3At5-6AcB9Wj3AK4=YcR8f6w@mail.gmail.com>
Date:   Fri, 28 Aug 2020 10:17:14 +0530
From:   Anup Patel <anup@...infault.org>
To:     Yifei Jiang <jiangyifei@...wei.com>
Cc:     Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Anup Patel <anup.patel@....com>,
        Alistair Francis <alistair.francis@....com>,
        Atish Patra <atish.patra@....com>, deepa.kernel@...il.com,
        kvm-riscv@...ts.infradead.org, KVM General <kvm@...r.kernel.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
        "Zhangxiaofeng (F)" <victor.zhangxiaofeng@...wei.com>,
        wu.wubin@...wei.com,
        Zhanghailiang <zhang.zhanghailiang@...wei.com>,
        "dengkai (A)" <dengkai1@...wei.com>,
        yinyipeng <yinyipeng1@...wei.com>
Subject: Re: [PATCH RFC 1/2] riscv/kvm: Fix use VSIP_VALID_MASK mask HIP register

On Thu, Aug 27, 2020 at 1:53 PM Yifei Jiang <jiangyifei@...wei.com> wrote:
>
> The correct sip/sie 0x222 could mask wrong 0x000 by VSIP_VALID_MASK,
> This patch fix it.
>
> Signed-off-by: Yifei Jiang <jiangyifei@...wei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@...wei.com>
> ---
>  arch/riscv/kvm/vcpu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index adb0815951aa..2976666e921f 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -419,8 +419,8 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *vcpu,
>
>         if (reg_num == KVM_REG_RISCV_CSR_REG(sip) ||
>             reg_num == KVM_REG_RISCV_CSR_REG(sie)) {
> -               reg_val = reg_val << VSIP_TO_HVIP_SHIFT;
>                 reg_val = reg_val & VSIP_VALID_MASK;
> +               reg_val = reg_val << VSIP_TO_HVIP_SHIFT;

Thanks for this fix. I have squashed it into PATCH5 of KVM RISC-V v14
series.

Regards,
Anup