linux-kernel - [PATCH 1/1] ARM: dts: bcm2711: Enable ddr modes on emmc2 controller

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Date:   Sun, 30 Aug 2020 01:15:09 +0200
From:   Tobias Schramm <t.schramm@...jaro.org>
To:     Rob Herring <robh+dt@...nel.org>,
        Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
Cc:     devicetree@...r.kernel.org, bcm-kernel-feedback-list@...adcom.com,
        linux-kernel@...r.kernel.org,
        Tobias Schramm <t.schramm@...jaro.org>
Subject: [PATCH 1/1] ARM: dts: bcm2711: Enable ddr modes on emmc2 controller

This patch enables ddr modes for eMMC and SD storage on emmc2,
doubling transfer speed. Previously only single data rate modes were
used, wasting half the available throughput.
The bcm2711 supports both SD and eMMC storage using ddr modes. Testing
show that pcb layout of the Raspberry Pi 4 can support them, too.

Signed-off-by: Tobias Schramm <t.schramm@...jaro.org>
---
 arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
index 222d7825e1ab..8b61e258e906 100644
--- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
@@ -191,6 +191,8 @@ &emmc2 {
 	vqmmc-supply = <&sd_io_1v8_reg>;
 	vmmc-supply = <&sd_vcc_reg>;
 	broken-cd;
+	mmc-ddr-3_3v;
+	sd-uhs-ddr50;
 	status = "okay";
 };
 
-- 
2.28.0