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Message-Id: <20200831073101.3608-3-m.cerveny@computer.org>
Date:   Mon, 31 Aug 2020 09:31:00 +0200
From:   Martin Cerveny <m.cerveny@...puter.org>
To:     Corentin Labbe <clabbe.montjoie@...il.com>
Cc:     Martin Cerveny <m.cerveny@...puter.org>,
        Chen-Yu Tsai <wens@...e.org>,
        "David S. Miller" <davem@...emloft.net>,
        devicetree@...r.kernel.org,
        Herbert Xu <herbert@...dor.apana.org.au>,
        linux-arm-kernel@...ts.infradead.org, linux-crypto@...r.kernel.org,
        linux-kernel@...r.kernel.org, Maxime Ripard <mripard@...nel.org>,
        Rob Herring <robh+dt@...nel.org>
Subject: [PATCH v2 2/3] ARM: dts: sun8i: v3s: Enable crypto engine

V3s contains crypto engine that is compatible with "sun4i-ss".

Tested-by: Martin Cerveny <m.cerveny@...puter.org>
Signed-off-by: Martin Cerveny <m.cerveny@...puter.org>
---
 arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index e5312869c..4fec84c40 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -234,6 +234,16 @@
 			#size-cells = <0>;
 		};
 
+		crypto: crypto@...5000 {
+			compatible = "allwinner,sun8i-v3s-crypto";
+			reg = <0x01c15000 0x1000>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_CE>;
+			reset-names = "ahb";
+		};
+
 		usb_otg: usb@...9000 {
 			compatible = "allwinner,sun8i-h3-musb";
 			reg = <0x01c19000 0x0400>;
-- 
2.17.1

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