linux-kernel - Re: [PATCH 2/2] mtd: spi-nor: enable lock interface for macronix chips

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <ae094597-e57e-dff1-f897-bf3cc75f5511@prevas.dk>
Date:   Mon, 31 Aug 2020 12:55:16 +0200
From:   Rasmus Villemoes <rasmus.villemoes@...vas.dk>
To:     Ivan Mikhaylov <i.mikhaylov@...ro.com>
Cc:     Tudor Ambarus <tudor.ambarus@...rochip.com>,
        Miquel Raynal <miquel.raynal@...tlin.com>,
        Richard Weinberger <richard@....at>,
        Vignesh Raghavendra <vigneshr@...com>,
        linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] mtd: spi-nor: enable lock interface for macronix
 chips

On 12/08/2020 17.18, Ivan Mikhaylov wrote:
> Add locks for whole macronix chip series with BP0-2 and BP0-3 bits.
> 
> Tested with mx25l51245g(BP0-3).

Hmm. I've tried adding support for locking on Macronix to U-Boot
(https://patchwork.ozlabs.org/project/uboot/patch/20200326114257.1782-3-rasmus.villemoes@prevas.dk/),
but that was quite a bit more involved than this. Note in particular the
first part of my commit message:

  Macronix chips implements locking in (power-of-two multiple of) 64K
  blocks, not as a fraction of the chip's size.

At least, that was true for the chip I was interested in and the few
others whose data sheets I grabbed to double-check. So I'm a bit
skeptical that this can work out-of-the-box without introducing a new
struct spi_nor_locking_ops.

Rasmus