linux-kernel - [PATCH 1/4] perf vendor events amd: Add L2 Prefetch events for zen1

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Message-Id: <20200901220944.277505-1-kim.phillips@amd.com>
Date:   Tue,  1 Sep 2020 17:09:41 -0500
From:   Kim Phillips <kim.phillips@....com>
To:     Arnaldo Carvalho de Melo <acme@...hat.com>, kim.phillips@....com
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>,
        Vijay Thakkar <vijaythakkar@...com>,
        Andi Kleen <ak@...ux.intel.com>,
        John Garry <john.garry@...wei.com>,
        Kan Liang <kan.liang@...ux.intel.com>,
        Yunfeng Ye <yeyunfeng@...wei.com>,
        Jin Yao <yao.jin@...ux.intel.com>,
        Martin Liška <mliska@...e.cz>,
        Borislav Petkov <bp@...e.de>, Jon Grimm <jon.grimm@....com>,
        Martin Jambor <mjambor@...e.cz>,
        Michael Petlan <mpetlan@...hat.com>,
        William Cohen <wcohen@...hat.com>,
        Stephane Eranian <eranian@...gle.com>,
        Ian Rogers <irogers@...gle.com>,
        linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org,
        stable@...r.kernel.org
Subject: [PATCH 1/4] perf vendor events amd: Add L2 Prefetch events for zen1

Later revisions of PPRs that post-date the original Family 17h events
submission patch add these events.

Specifically, they were not in this 2017 revision of the F17h PPR:

Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors Rev 1.14 - April 15, 2017

But e.g., are included in this 2019 version of the PPR:

Processor Programming Reference (PPR) for AMD Family 17h Model 18h, Revision B1 Processors Rev. 3.14 - Sep 26, 2019

Signed-off-by: Kim Phillips <kim.phillips@....com>
Fixes: 98c07a8f74f8 ("perf vendor events amd: perf PMU events for AMD Family 17h")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Ingo Molnar <mingo@...hat.com>
Cc: Arnaldo Carvalho de Melo <acme@...nel.org>
Cc: Mark Rutland <mark.rutland@....com>
Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Jiri Olsa <jolsa@...hat.com>
Cc: Namhyung Kim <namhyung@...nel.org>
Cc: Vijay Thakkar <vijaythakkar@...com>
Cc: Andi Kleen <ak@...ux.intel.com>
Cc: John Garry <john.garry@...wei.com>
Cc: Kan Liang <kan.liang@...ux.intel.com>
Cc: Yunfeng Ye <yeyunfeng@...wei.com>
Cc: Jin Yao <yao.jin@...ux.intel.com>
Cc: "Martin Liška" <mliska@...e.cz>
Cc: Borislav Petkov <bp@...e.de>
Cc: Jon Grimm <jon.grimm@....com>
Cc: Martin Jambor <mjambor@...e.cz>
Cc: Michael Petlan <mpetlan@...hat.com>
Cc: William Cohen <wcohen@...hat.com>
Cc: Stephane Eranian <eranian@...gle.com>
Cc: Ian Rogers <irogers@...gle.com>
Cc: linux-perf-users@...r.kernel.org
Cc: linux-kernel@...r.kernel.org
Cc: stable@...r.kernel.org
---
 .../pmu-events/arch/x86/amdzen1/cache.json     | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/tools/perf/pmu-events/arch/x86/amdzen1/cache.json b/tools/perf/pmu-events/arch/x86/amdzen1/cache.json
index 404d4c569c01..695ed3ffa3a6 100644
--- a/tools/perf/pmu-events/arch/x86/amdzen1/cache.json
+++ b/tools/perf/pmu-events/arch/x86/amdzen1/cache.json
@@ -249,6 +249,24 @@
     "BriefDescription": "Cycles with fill pending from L2. Total cycles spent with one or more fill requests in flight from L2.",
     "UMask": "0x1"
   },
+  {
+    "EventName": "l2_pf_hit_l2",
+    "EventCode": "0x70",
+    "BriefDescription": "L2 prefetch hit in L2.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_hit_l3",
+    "EventCode": "0x71",
+    "BriefDescription": "L2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit the L3.",
+    "UMask": "0xff"
+  },
+  {
+    "EventName": "l2_pf_miss_l2_l3",
+    "EventCode": "0x72",
+    "BriefDescription": "L2 prefetcher misses in L3. All L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches.",
+    "UMask": "0xff"
+  },
   {
     "EventName": "l3_request_g1.caching_l3_cache_accesses",
     "EventCode": "0x01",
-- 
2.27.0