| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Tue, 1 Sep 2020 09:38:01 +0100
From: Leo Yan <leo.yan@...aro.org>
To: Arnaldo Carvalho de Melo <acme@...nel.org>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...hat.com>,
Namhyung Kim <namhyung@...nel.org>,
Adrian Hunter <adrian.hunter@...el.com>,
Andi Kleen <ak@...ux.intel.com>,
Ian Rogers <irogers@...gle.com>,
Nick Desaulniers <ndesaulniers@...gle.com>,
"Naveen N. Rao" <naveen.n.rao@...ux.vnet.ibm.com>,
Kemeng Shi <shikemeng@...wei.com>,
James Clark <james.clark@....com>,
Wei Li <liwei391@...wei.com>, Al Grant <Al.Grant@....com>,
Will Deacon <will@...nel.org>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Mike Leach <mike.leach@...aro.org>,
linux-kernel@...r.kernel.org
Cc: Leo Yan <leo.yan@...aro.org>
Subject: [PATCH v2 00/14] perf mem: Support AUX trace and Arm SPE
This patch set is to support AUX trace and Arm SPE as the first enabled
hardware tracing for Perf memory tool.
Patches 01 ~ 04 are preparasion patches which mainly resolve the issue
for memory events, since the existed code is hard coded the memory
events which based on x86 and PowerPC architectures, so patches 01 ~ 04
extend to support more flexible memory event name, and introduce weak
functions so can allow every architecture to define its own memory
events structure and returning event pointer and name respectively.
Patches 05 and 06 are used to extend Perf memory tool to support AUX
trace, and add a new option 'M' for itrace for generate memory events.
Patches 07 ~ 13 are to support Arm SPE with Perf memory tool. Firstly it
registers SPE events for memory events, then it extends the SPE packet
to pass addresses info and operation types, and also set 'data_src'
field so can allow the tool to display readable string in the result.
Patch 14 is to update documentation to reflect changes introduced for
support Arm SPE.
This patch set has been tested on ARMv8 Hisilicon D06 platform and
verfied on x86 so avoid to cause regression. Please note, this patch
set is dependent on the patch set "perf arm-spe: Refactor decoding &
dumping flow" [1].
Below commands can run successfully on D06:
$ perf mem record -t ldst -- ~/false_sharing.exe 2
$ perf mem record -t load -- ~/false_sharing.exe 2
$ perf mem record -t store -- ~/false_sharing.exe 2
$ perf mem report
$ perf mem report --itrace=M
# Samples: 391K of event 'memory'
# Total weight : 391193
# Sort order : local_weight,mem,sym,dso,symbol_daddr,dso_daddr,snoop,tlb,locked
#
# Overhead Samples Local Weight Memory access Symbol Shared Object Data Symbol Data Object Snoop TLB access Locked
# ........ ............ ............ ........................ ............................................... .................. ............................................................ ................. ............ ...................... ......
#
18.56% 72611 0 L1 or L1 miss [.] read_write_func false_sharing.exe [.] buf1+0x0 false_sharing.exe N/A Walker hit No
16.16% 63207 0 L1 or L1 hit [.] read_write_func false_sharing.exe [.] __do_global_dtors_aux_fini_array_entry+0x228 false_sharing.exe N/A Walker hit No
15.91% 62239 0 L1 or L1 hit [.] read_write_func false_sharing.exe [.] __do_global_dtors_aux_fini_array_entry+0x250 false_sharing.exe N/A Walker hit No
4.67% 18280 0 N/A [.] read_write_func false_sharing.exe [.] buf2+0x8 false_sharing.exe N/A Walker hit No
3.34% 13082 0 L1 or L1 hit [.] read_write_func false_sharing.exe [.] __do_global_dtors_aux_fini_array_entry+0x230 false_sharing.exe N/A Walker hit No
2.49% 9755 0 L1 or L1 hit [.] read_write_func false_sharing.exe [.] 0x0000aaaac23a3450 false_sharing.exe N/A Walker hit No
2.46% 9611 0 L1 or L1 hit [.] read_write_func false_sharing.exe [.] lock_thd_name+0x0 false_sharing.exe N/A Walker hit No
2.26% 8856 0 L1 or L1 hit [.] read_write_func false_sharing.exe [.] 0x0000aaaac23a3458 false_sharing.exe N/A Walker hit No
2.19% 8549 0 L1 or L1 miss [.] read_write_func false_sharing.exe [.] buf2+0x28 false_sharing.exe N/A Walker hit No
Changes from v1:
* Refined patch 02 to use perf_mem_events__ptr() to return event pointer
and check if pointer is NULL, and remove the condition checking for
PERF_MEM_EVENTS__MAX; (James Clark)
* Added new itrace option 'M' for memory events;
* Added patch 14 to update documentation.
[1] https://lore.kernel.org/patchwork/cover/1288406/
Leo Yan (14):
perf mem: Search event name with more flexible path
perf mem: Introduce weak function perf_mem_events__ptr()
perf mem: Support new memory event PERF_MEM_EVENTS__LOAD_STORE
perf mem: Only initialize memory event for recording
perf auxtrace: Add option '-M' for memory events
perf mem: Support AUX trace
perf mem: Support Arm SPE events
perf arm-spe: Enable attribution PERF_SAMPLE_DATA_SRC
perf arm-spe: Save memory addresses in packet
perf arm-spe: Store operation types in packet
perf arm-spe: Fill address info for samples
perf arm-spe: Synthesize memory event
perf arm-spe: Set sample's data source field
perf mem: Document options introduced by Arm SPE
tools/perf/Documentation/itrace.txt | 1 +
tools/perf/Documentation/perf-mem.txt | 10 +-
tools/perf/arch/arm64/util/Build | 2 +-
tools/perf/arch/arm64/util/mem-events.c | 46 ++++++
tools/perf/builtin-c2c.c | 23 ++-
tools/perf/builtin-mem.c | 73 ++++++++--
.../util/arm-spe-decoder/arm-spe-decoder.c | 15 ++
.../util/arm-spe-decoder/arm-spe-decoder.h | 8 ++
tools/perf/util/arm-spe.c | 132 +++++++++++++++---
tools/perf/util/auxtrace.c | 4 +
tools/perf/util/auxtrace.h | 2 +
tools/perf/util/mem-events.c | 41 ++++--
tools/perf/util/mem-events.h | 3 +-
13 files changed, 302 insertions(+), 58 deletions(-)
create mode 100644 tools/perf/arch/arm64/util/mem-events.c
--
2.20.1
Powered by blists - more mailing lists