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Message-ID: <C5EFA1CC-311C-47D5-9506-D087D9AE58D1@nvidia.com>
Date: Wed, 2 Sep 2020 15:05:39 -0400
From: Zi Yan <ziy@...dia.com>
To: Jason Gunthorpe <jgg@...pe.ca>
CC: <linux-mm@...ck.org>, Roman Gushchin <guro@...com>,
Rik van Riel <riel@...riel.com>,
"Kirill A . Shutemov" <kirill.shutemov@...ux.intel.com>,
Matthew Wilcox <willy@...radead.org>,
Shakeel Butt <shakeelb@...gle.com>,
Yang Shi <yang.shi@...ux.alibaba.com>,
David Nellans <dnellans@...dia.com>,
<linux-kernel@...r.kernel.org>
Subject: Re: [RFC PATCH 00/16] 1GB THP support on x86_64
On 2 Sep 2020, at 14:48, Jason Gunthorpe wrote:
> On Wed, Sep 02, 2020 at 02:45:37PM -0400, Zi Yan wrote:
>
>>> Surprised this doesn't touch mm/pagewalk.c ?
>>
>> 1GB PUD page support is present for DAX purpose, so the code is there
>> in mm/pagewalk.c already. I only needed to supply ops->pud_entry when using
>> the functions in mm/pagewalk.c. :)
>
> Yes, but doesn't this change what is possible under the mmap_sem
> without the page table locks?
>
> ie I would expect some thing like pmd_trans_unstable() to be required
> as well for lockless walkers. (and I don't think the pmd code is 100%
> right either)
>
Right. I missed that. Thanks for pointing it out.
The code like this, right?
diff --git a/mm/pagewalk.c b/mm/pagewalk.c
index e81640d9f177..4fe6ce4a92eb 100644
--- a/mm/pagewalk.c
+++ b/mm/pagewalk.c
@@ -152,10 +152,11 @@ static int walk_pud_range(p4d_t *p4d, unsigned long addr, unsigned long end,
!(ops->pmd_entry || ops->pte_entry))
continue;
- if (walk->vma)
+ if (walk->vma) {
split_huge_pud(walk->vma, pud, addr);
- if (pud_none(*pud))
- goto again;
+ if (pud_trans_unstable(pud))
+ goto again;
+ }
err = walk_pmd_range(pud, addr, next, walk);
if (err)
—
Best Regards,
Yan Zi
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