linux-kernel - RE: [PATCH v2] x86/asm: Replace __force

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <41d1eec58dd54d878710cbb6121feecf@AcuMS.aculab.com>
Date:   Wed, 2 Sep 2020 20:26:06 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Arvind Sankar' <nivedita@...m.mit.edu>
CC:     Linus Torvalds <torvalds@...ux-foundation.org>,
        Miguel Ojeda <miguel.ojeda.sandonis@...il.com>,
        Sedat Dilek <sedat.dilek@...il.com>,
        Segher Boessenkool <segher@...nel.crashing.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Nick Desaulniers <ndesaulniers@...gle.com>,
        "Paul E. McKenney" <paulmck@...nel.org>,
        Ingo Molnar <mingo@...hat.com>, Arnd Bergmann <arnd@...db.de>,
        Borislav Petkov <bp@...en8.de>,
        "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@...nel.org>,
        "H. Peter Anvin" <hpa@...or.com>,
        "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
        Kees Cook <keescook@...omium.org>,
        Peter Zijlstra <peterz@...radead.org>,
        Juergen Gross <jgross@...e.com>,
        Andy Lutomirski <luto@...nel.org>,
        Andrew Cooper <andrew.cooper3@...rix.com>,
        LKML <linux-kernel@...r.kernel.org>,
        clang-built-linux <clang-built-linux@...glegroups.com>,
        Will Deacon <will@...nel.org>,
        "nadav.amit@...il.com" <nadav.amit@...il.com>,
        "Nathan Chancellor" <natechancellor@...il.com>
Subject: RE: [PATCH v2] x86/asm: Replace __force_order with memory clobber

From: Arvind Sankar
> Sent: 02 September 2020 17:08
> 
> On Wed, Sep 02, 2020 at 11:33:46AM -0400, Arvind Sankar wrote:
> > Fix this by:
> > - Using a memory clobber for the write functions to additionally prevent
> >   caching/reordering memory accesses across CRn writes.
> > - Using a dummy input operand with an arbitrary constant address for the
> >   read functions, instead of a global variable. This will prevent reads
> >   from being reordered across writes, while allowing memory loads to be
> >   cached/reordered across CRn reads, which should be safe.
> >
> 
> Any thoughts on whether FORCE_ORDER is worth it just for CRn? MSRs don't
> use it, Nadav pointed out that PKRU doesn't use it (PKRU doesn't have a
> memory clobber on write either). I would guess that most of the volatile
> asm has not been written with the assumption that the compiler might
> decide to reorder it, so protecting just CRn access doesn't mitigate the
> impact of this bug.

I'm guessing that __force_order memory reference was added because
the compiler managed to reorder a particular pair of accesses.

However writing to some of the CR (and maybe MSR) has side effects
on other memory accesses - so should really have a full "memory" clobber.

OTOH none of the CR or MSR access are common, and I suspect a lot
are slow to execute (even if not actually serialising).
So a 'belt and braces' "memory" clobber that definitely stops the
compiler re-ordering instructions across the access avoids
any possible unwanted effects.

After all, any such code is really 'assembler written in C'.

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)