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Message-Id: <20200902230215.3452712-1-swboyd@chromium.org>
Date: Wed, 2 Sep 2020 16:02:05 -0700
From: Stephen Boyd <swboyd@...omium.org>
To: Kishon Vijay Abraham I <kishon@...com>,
Vinod Koul <vkoul@...nel.org>
Cc: linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
Jeykumar Sankaran <jsanka@...eaurora.org>,
Chandan Uddaraju <chandanu@...eaurora.org>,
Vara Reddy <varar@...eaurora.org>,
Tanmay Shah <tanmay@...eaurora.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Manu Gautam <mgautam@...eaurora.org>,
Sandeep Maheswaram <sanm@...eaurora.org>,
Douglas Anderson <dianders@...omium.org>,
Sean Paul <seanpaul@...omium.org>,
Rob Clark <robdclark@...omium.org>,
Jonathan Marek <jonathan@...ek.ca>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
devicetree@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
Stephen Boyd <sboyd@...nel.org>
Subject: [PATCH v2 00/10] Support qcom USB3+DP combo phy (or type-c phy)
This patch series is based on v12 of the msm DP driver submission[1]
plus a compliance patch[2]. In the v5 patch series review I suggested
that the DP PHY and PLL be split out of the drm driver and moved to the
qmp phy driver. This patch series does that, but it is still marked as
an RFC because there are a couple more things to do, mostly updating the
DT binding and getting agreement on how to structure the code.
Eventually I believe the qmp phy driver will need to listen for type-c
notifiers or somehow know the type-c pinout being used so this driver
can program things slightly differently. Right now, I don't have any way
to test it though, so I've left it as future work. For some more
details, the DP phy and the USB3 phy share the same physical pins on the
SoC and those pins pretty much line up with a type-c pinout modulo some
CC pins for cable orientation detection logic that lives on the PMIC. So
the DP phy can use all four lanes or it can use two lanes and the USB3
phy can use two lanes. In the hardware designs that I have access to it
is always two lanes for USB3 and two lanes for DP going through what
looks like a type-c pinout so this just hard codes that configuration in
the driver.
Here's the example node that I'm using on sc7180:
usb_1_qmpphy: phy-wrapper@...9000 {
compatible = "qcom,sc7180-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>, // usb pll (or serdes)
<0 0x088e8000 0 0x38>, // dp com
<0 0x088ea000 0 0x40>; // dp pll (or serdes)
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: usb3-phy@...9200 {
reg = <0 0x088e9200 0 0x128>, // tx0
<0 0x088e9400 0 0x200>, // rx0
<0 0x088e9c00 0 0x218>, // pcs
<0 0x088e9600 0 0x128>, // tx1
<0 0x088e9800 0 0x200>, // rx1
<0 0x088e9a00 0 0x18>; // pcs misc
#clock-cells = <0>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
dp_phy: dp-phy@...a200 {
reg = <0 0x088ea200 0 0x200>, // tx0
<0 0x088ea400 0 0x200>, // rx0
<0 0x088eaa00 0 0x200>, // dp phy
<0 0x088ea600 0 0x200>, // tx1
<0 0x088ea800 0 0x200>; // rx1
#clock-cells = <1>;
#phy-cells = <0>;
};
};
I had to put the serdes register region in the wrapper node and jam the
common area (dp_com) in the middle. Sort of a mess but it was the best I
could do to make the driver changes minimially invasive. I also had to
change the node names to 'usb3-phy' and 'dp-phy' from 'phy' so that I
could differentiate the different phys in the driver. Otherwise the qmp
driver was already mostly prepared for two different phys to sit next to
each other inside the phy wrapper so it was mostly just a chore of
moving code from one place to another.
The last patch in this series rips out the DP PHY and PLL code from the
drm driver and wires in the phy API calls instead. I don't know the
merge path for it. Maybe Rob Clark can pick it up and I can pick the clk
patch into clk-next and the phy patches can go via the phy tree, then
everything can meet in linux-next. There are still some more TODOs in
the code but they feel minor enough to fix with more testing.
Changes from v1 (https://lore.kernel.org/r/20200826024711.220080-1-swboyd@chromium.org)
* New patch for devm_platform_ioremap_resource()
* Moved serdes tables to sc7180 patch
* Removed more dead code from drm driver in last patch
* Reset aux phy is kept around now. Slightly moved where we init the
phy and setup aux
* Added a phy_exit() call to last patch so we properly shut down DP on
disconnect and can work on multiple plugs
Changes from RFC (https://lore.kernel.org/r/20200611091919.108018-1-swboyd@chromium.org)
* New patch for DT binding
* Rebased onto latest DP patch series
TODO:
* Clean up phy power on sequence a bit so that it is done in one place
instead of two
* Allow link rate to change after phy is powered on?
* Make the runtime PM logic detect combo phy and power down both?
Stephen Boyd (10):
dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information
phy: qcom-qmp: Move phy mode into struct qmp_phy
phy: qcom-qmp: Remove 'initialized' in favor of 'init_count'
phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy'
phy: qcom-qmp: Get dp_com I/O resource by index
phy: qcom-qmp: Use devm_platform_ioremap_resource() to simplify
phy: qcom-qmp: Add support for DP in USB3+DP combo phy
phy: qcom-qmp: Add support for sc7180 DP phy
clk: qcom: dispcc: Update DP clk ops for phy design
drm/msm/dp: Use qmp phy for DP PLL and PHY
.../bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 91 +-
drivers/clk/qcom/clk-rcg2.c | 19 +-
drivers/clk/qcom/dispcc-sc7180.c | 3 -
drivers/gpu/drm/msm/Makefile | 4 +-
drivers/gpu/drm/msm/dp/dp_aux.c | 7 +-
drivers/gpu/drm/msm/dp/dp_catalog.c | 287 +----
drivers/gpu/drm/msm/dp/dp_catalog.h | 9 +-
drivers/gpu/drm/msm/dp/dp_ctrl.c | 48 +-
drivers/gpu/drm/msm/dp/dp_display.c | 17 -
drivers/gpu/drm/msm/dp/dp_display.h | 3 -
drivers/gpu/drm/msm/dp/dp_link.c | 2 +
drivers/gpu/drm/msm/dp/dp_panel.c | 1 +
drivers/gpu/drm/msm/dp/dp_parser.c | 12 +-
drivers/gpu/drm/msm/dp/dp_parser.h | 12 +-
drivers/gpu/drm/msm/dp/dp_pll.c | 99 --
drivers/gpu/drm/msm/dp/dp_pll.h | 61 -
drivers/gpu/drm/msm/dp/dp_pll_10nm.c | 930 ---------------
drivers/gpu/drm/msm/dp/dp_pll_private.h | 89 --
drivers/gpu/drm/msm/dp/dp_power.c | 39 +-
drivers/gpu/drm/msm/dp/dp_power.h | 9 -
drivers/gpu/drm/msm/dp/dp_reg.h | 213 ----
drivers/phy/qualcomm/phy-qcom-qmp.c | 1057 ++++++++++++++---
drivers/phy/qualcomm/phy-qcom-qmp.h | 80 ++
23 files changed, 1140 insertions(+), 1952 deletions(-)
delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll.c
delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll.h
delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll_10nm.c
delete mode 100644 drivers/gpu/drm/msm/dp/dp_pll_private.h
Cc: Jeykumar Sankaran <jsanka@...eaurora.org>
Cc: Chandan Uddaraju <chandanu@...eaurora.org>
Cc: Vara Reddy <varar@...eaurora.org>
Cc: Tanmay Shah <tanmay@...eaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@...aro.org>
Cc: Manu Gautam <mgautam@...eaurora.org>
Cc: Sandeep Maheswaram <sanm@...eaurora.org>
Cc: Douglas Anderson <dianders@...omium.org>
Cc: Sean Paul <seanpaul@...omium.org>
Cc: Rob Clark <robdclark@...omium.org>
Cc: Jonathan Marek <jonathan@...ek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Cc: <devicetree@...r.kernel.org>
Cc: Rob Herring <robh+dt@...nel.org>
Cc: Stephen Boyd <sboyd@...nel.org>
[1] https://lore.kernel.org/r/20200827211658.27479-1-tanmay@codeaurora.org
[2] https://lore.kernel.org/r/20200827214739.22037-1-khsieh@codeaurora.org
base-commit: d012a7190fc1fd72ed48911e77ca97ba4521bccd
prerequisite-patch-id: aa650e8353e003be0075deea0dee92a82e321432
prerequisite-patch-id: 496af774194db20706fa82eb79f95891c8784952
prerequisite-patch-id: 87e6b1a10063ca350cacd64408024714599a14f4
prerequisite-patch-id: ac467cb99ea60ee186ab9bbe47a3e4d9c13a1313
prerequisite-patch-id: 4eff0531912abbfa748181e90baffba9eb52e295
prerequisite-patch-id: a6970d668b3570f2c10eda99904aa3dfc8fefa1d
--
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