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Message-ID: <4b17cace-09d5-af8c-6e7f-9358cfdceb4d@ti.com>
Date: Wed, 2 Sep 2020 13:07:33 +0530
From: Kishon Vijay Abraham I <kishon@...com>
To: Nishanth Menon <nm@...com>, Rob Herring <robh+dt@...nel.org>
CC: Tero Kristo <t-kristo@...com>,
<linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [RESEND PATCH 1/2] arm64: dts: ti: k3-j721e-main: Add PCIe device
tree nodes
Hi Rob,
On 02/09/20 10:24 am, Kishon Vijay Abraham I wrote:
> Hi Nishanth,
>
> On 01/09/20 8:22 pm, Nishanth Menon wrote:
>> On 19:36-20200901, Kishon Vijay Abraham I wrote:
>>> Add PCIe device tree node (both RC and EP) for the four
>>> PCIe instances here.
>>>
>>> Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
>>> ---
>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 218 ++++++++++++++++++++++
>>> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 5 +-
>>> 2 files changed, 222 insertions(+), 1 deletion(-)
>>
>>
>> Did you look at the diff of the dtbs_check before and after this
>> series? I see: https://pastebin.ubuntu.com/p/9fyfrTjx9M/
>
> I didn't see any errors when I checked for individual bindings
> a0393678@...93678-ssd:~/repos/linux$ mkconfig64 dtbs_check
> DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml"
>
> SCHEMA Documentation/devicetree/bindings/processed-schema.yaml
> DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml
> DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml
> CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml
> CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml
> a0393678@...93678-ssd:~/repos/linux$ mkconfig64 dtbs_check
> DT_SCHEMA_FILES="Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml"
>
> SCHEMA Documentation/devicetree/bindings/processed-schema.yaml
> DTC arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml
> DTC arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml
> CHECK arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml
> CHECK arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dt.yaml
Can you give hint on why I get ranges is too long error
https://pastebin.ubuntu.com/p/cPm2tg3dcV/ which I give mkconfig64
dtbs_check but don't see an error when I include "DT_SCHEMA_FILES"?
Thanks
Kishon
>>
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> index 00a36a14efe7..a36909d8b8c3 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>> @@ -28,6 +28,26 @@
>>> #size-cells = <1>;
>>> ranges = <0x0 0x0 0x00100000 0x1c000>;
>>> + pcie0_ctrl: pcie-ctrl@...0 {
>> https://github.com/devicetree-org/devicetree-specification/releases/download/v0.3/devicetree-specification-v0.3.pdf
>>
>> Section 2.2.2: why not use syscon@...0 and so on?
>
> okay, will change to generic name.
>>
>>> + compatible = "syscon";
>>> + reg = <0x00004070 0x4>;
>>> + };
>>> +
>>> + pcie1_ctrl: pcie-ctrl@...4 {
>>> + compatible = "syscon";
>>> + reg = <0x00004074 0x4>;
>>> + };
>>> +
>>> + pcie2_ctrl: pcie-ctrl@...8 {
>>> + compatible = "syscon";
>>> + reg = <0x00004078 0x4>;
>>> + };
>>> +
>>> + pcie3_ctrl: pcie-ctrl@...c {
>>> + compatible = "syscon";
>>> + reg = <0x0000407c 0x4>;
>>> + };
>>> +
>>> serdes_ln_ctrl: serdes-ln-ctrl@...0 {
>>> compatible = "mmio-mux";
>>> reg = <0x00004080 0x50>;
>>> @@ -576,6 +596,204 @@
>>> };
>>> };
>>> + pcie0_rc: pcie@...0000 {
>>> + compatible = "ti,j721e-pcie-host";
>>> + reg = <0x00 0x02900000 0x00 0x1000>,
>>> + <0x00 0x02907000 0x00 0x400>,
>>> + <0x00 0x0d000000 0x00 0x00800000>,
>>> + <0x00 0x10000000 0x00 0x00001000>;
>>> + reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
>>> + interrupt-names = "link_state";
>>> + interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
>>> + device_type = "pci";
>>> + ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
>>> + max-link-speed = <3>;
>>> + num-lanes = <2>;
>>> + power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
>>> + clocks = <&k3_clks 239 1>;
>>> + clock-names = "fck";
>>> + #address-cells = <3>;
>>> + #size-cells = <2>;
>>> + bus-range = <0x0 0xf>;
>>> + vendor-id = <0x104c>;
>>> + device-id = <0xb00d>;
>>> + msi-map = <0x0 &gic_its 0x0 0x10000>;
>>> + dma-coherent;
>>> + ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0
>>> 0x0010000>,
>>> + <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
>>> + dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>>> + };
>>> +
>>> + pcie0_ep: pcie-ep@...0000 {
>> Not related to this patch, but just a suggestion: pcie-ep -> do we
>> need to add that to the Generic names in DT spec?
>>
>> [...]
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
>>> b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
>>> index f787aa73aaae..eeb02115b966 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
>>> @@ -132,9 +132,12 @@
>>> <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /*
>>> USBSS1 */
>>> <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /*
>>> Most peripherals */
>>> <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /*
>>> MAIN NAVSS */
>>> - <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /*
>>> PCIe Core*/
>>> + <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /*
>>> PCIe Core*/
>>> + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /*
>>> PCIe Core*/
>>> <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /*
>>> PCIe DAT */
>> ^^
>> should be PCIe1?
>> Just because you are introducing PCIe2,3 in this patch, the net result
>> does'nt look consistent? Also might want to cover this change in the
>> $commit_message.
>
> yeah, we could have a separate patch for this change.
>
> Thanks
> Kishon
>
>> [...]
>>> <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /*
>>> C71 */
>>> + <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /*
>>> PCIe2 DAT */
>>> + <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /*
>>> PCIe3 DAT */
>>> <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /*
>>> C66_0 */
>>> <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /*
>>> C66_1 */
>>> <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /*
>>> GPU */
>>> --
>>> 2.17.1
>>>
>>
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