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Message-Id: <1599158501-8302-2-git-send-email-grzegorz.jaszczyk@linaro.org>
Date: Thu, 3 Sep 2020 20:41:40 +0200
From: Grzegorz Jaszczyk <grzegorz.jaszczyk@...aro.org>
To: ssantosh@...nel.org, s-anna@...com
Cc: grzegorz.jaszczyk@...aro.org, santosh.shilimkar@...cle.com,
robh+dt@...nel.org, lee.jones@...aro.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-omap@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
praneeth@...com, tony@...mide.com
Subject: [PATCH 1/2] dt-bindings: soc: ti: Update TI PRUSS bindings regarding clock-muxes
ICSS/ICSSG modules have an IEP clock mux that allow selection of
internal IEP clock from 2 clock sources.
ICSSG module has a CORE clock mux that allows selection of internal CORE
clock from 2 clock sources.
Add binding information for these 2 clock muxes.
Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@...aro.org>
---
.../devicetree/bindings/soc/ti/ti,pruss.yaml | 121 ++++++++++++++++++++-
1 file changed, 120 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
index a13e4df..037c51b 100644
--- a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
+++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
@@ -132,10 +132,99 @@ patternProperties:
- const: ti,pruss-cfg
- const: syscon
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
reg:
maxItems: 1
- additionalProperties: false
+ ranges:
+ maxItems: 1
+
+ clocks:
+ type: object
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ coreclk-mux@[a-f0-9]+$:
+ description: |
+ This is applicable only for ICSSG (K3 SoCs). The ICSSG modules
+ core clock can be set to one of the 2 sources: ICSSG_CORE_CLK or
+ ICSSG_ICLK. This node models this clock mux and should have the
+ name "coreclk-mux".
+
+ type: object
+
+ properties:
+ '#clock-cells':
+ const: 0
+
+ clocks:
+ items:
+ - description: ICSSG_CORE Clock
+ - description: ICSSG_ICLK Clock
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+ description: |
+ Standard assigned-clocks-parents definition used for selecting
+ mux parent (one of the mux input).
+
+ reg:
+ maxItems: 1
+
+ required:
+ - clocks
+
+ additionalProperties: false
+
+ iepclk-mux@[a-f0-9]+$:
+ description: |
+ The IEP module can get its clock from 2 sources: ICSSG_IEP_CLK or
+ CORE_CLK (OCP_CLK in older SoCs). This node models this clock
+ mux and should have the name "iepclk-mux".
+
+ type: object
+
+ properties:
+ '#clock-cells':
+ const: 0
+
+ clocks:
+ items:
+ - description: ICSSG_IEP Clock
+ - description: Core Clock (OCP Clock in older SoCs)
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+ description: |
+ Standard assigned-clocks-parents definition used for selecting
+ mux parent (one of the mux input).
+
+ reg:
+ maxItems: 1
+
+ required:
+ - clocks
+
+ additionalProperties: false
+
+ additionalProperties: false
iep@[a-f0-9]+$:
description: |
@@ -259,7 +348,22 @@ examples:
pruss_cfg: cfg@...00 {
compatible = "ti,pruss-cfg", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
reg = <0x26000 0x2000>;
+ ranges = <0x00 0x26000 0x2000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pruss_iepclk_mux: iepclk-mux@30 {
+ reg = <0x30>;
+ #clock-cells = <0>;
+ clocks = <&l3_gclk>, /* icss_iep */
+ <&pruss_ocp_gclk>; /* icss_ocp */
+ };
+ };
};
pruss_mii_rt: mii-rt@...00 {
@@ -298,7 +402,22 @@ examples:
pruss1_cfg: cfg@...00 {
compatible = "ti,pruss-cfg", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
reg = <0x26000 0x2000>;
+ ranges = <0x00 0x26000 0x2000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pruss1_iepclk_mux: iepclk-mux@30 {
+ reg = <0x30>;
+ #clock-cells = <0>;
+ clocks = <&sysclk_div>, /* icss_iep */
+ <&pruss_ocp_gclk>; /* icss_ocp */
+ };
+ };
};
pruss1_mii_rt: mii-rt@...00 {
--
2.7.4
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