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Message-Id: <26fe48b09d77088679ed0c8cb8cf0db2f108195e.1599120059.git-series.maxime@cerno.tech>
Date: Thu, 3 Sep 2020 10:01:02 +0200
From: Maxime Ripard <maxime@...no.tech>
To: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>,
Eric Anholt <eric@...olt.net>
Cc: dri-devel@...ts.freedesktop.org,
linux-rpi-kernel@...ts.infradead.org,
bcm-kernel-feedback-list@...adcom.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Dave Stevenson <dave.stevenson@...pberrypi.com>,
Tim Gover <tim.gover@...pberrypi.com>,
Phil Elwell <phil@...pberrypi.com>,
Maxime Ripard <maxime@...no.tech>,
Chanwoo Choi <cw00.choi@...sung.com>,
Hoegeun Kwon <hoegeun.kwon@...sung.com>,
Stefan Wahren <stefan.wahren@...e.com>
Subject: [PATCH v5 30/80] drm/vc4: crtc: Clear the PixelValve FIFO on disable
In order to avoid a stale pixel getting stuck on mode change or a disable
/ enable cycle, we need to make sure to flush the PV FIFO on disable.
Reviewed-by: Dave Stevenson <dave.stevenson@...pberrypi.com>
Tested-by: Chanwoo Choi <cw00.choi@...sung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@...sung.com>
Tested-by: Stefan Wahren <stefan.wahren@...e.com>
Signed-off-by: Maxime Ripard <maxime@...no.tech>
---
drivers/gpu/drm/vc4/vc4_crtc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 4c23cf8aefb9..73d918706f7e 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -424,8 +424,7 @@ static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
if (vc4_encoder->post_crtc_disable)
vc4_encoder->post_crtc_disable(encoder);
- CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
-
+ vc4_crtc_pixelvalve_reset(crtc);
vc4_hvs_atomic_disable(crtc, old_state);
if (vc4_encoder->post_crtc_powerdown)
--
git-series 0.9.1
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