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Message-ID: <CAHp75Vd3wjNHdYC_A1EVV+kzN=6SGqP2qQ0Wb6pdZWWt9qMMLw@mail.gmail.com>
Date:   Thu, 3 Sep 2020 14:01:08 +0300
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Shiju Jose <shiju.jose@...wei.com>
Cc:     Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        "linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "rjw@...ysocki.net" <rjw@...ysocki.net>,
        "helgaas@...nel.org" <helgaas@...nel.org>,
        "bp@...en8.de" <bp@...en8.de>,
        "james.morse@....com" <james.morse@....com>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "robh@...nel.org" <robh@...nel.org>,
        "lenb@...nel.org" <lenb@...nel.org>,
        "tony.luck@...el.com" <tony.luck@...el.com>,
        "dan.carpenter@...cle.com" <dan.carpenter@...cle.com>,
        yangyicong <yangyicong@...wei.com>,
        Jonathan Cameron <jonathan.cameron@...wei.com>,
        tanxiaofei <tanxiaofei@...wei.com>,
        Linuxarm <linuxarm@...wei.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [RESEND PATCH v14 2/2] PCI: hip: Add handling of HiSilicon HIP
 PCIe controller errors

On Thu, Sep 3, 2020 at 1:43 PM Shiju Jose <shiju.jose@...wei.com> wrote:
> >From: Andy Shevchenko [mailto:andriy.shevchenko@...ux.intel.com]
> >Sent: 01 September 2020 09:26
> >On Mon, Aug 31, 2020 at 10:26:06PM +0100, Shiju Jose wrote:
> >> From: Yicong Yang <yangyicong@...ilicon.com>

...

> >> +config PCIE_HISI_ERR
> >> +    depends on ACPI_APEI_GHES && (ARM64 || COMPILE_TEST)
> >
> >> +    depends on ACPI
> >
> >Isn't this implied by
> >       drivers/acpi/Kconfig:45:if ACPI
> >?
>
> This can be removed as  ACPI_APEI_GHES depends on ACPI.
>
> Do you have any other comments on this patch?

Nope. The rest is fine to me.

> >> +    bool "HiSilicon HIP PCIe controller error handling driver"
> >> +    help
> >> +      Say Y here if you want error handling support
> >> +      for the PCIe controller's errors on HiSilicon HIP SoCs

-- 
With Best Regards,
Andy Shevchenko

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