linux-kernel - Re: [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller

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Date:   Thu, 3 Sep 2020 12:18:01 +0100
From:   "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To:     Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
        Magnus Damm <magnus.damm@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 1/4] ARM: dts: r8a7742-iwg21d-q7: Enable PCIe Controller

Hi Geert,

Thank you for the review.

On Thu, Sep 3, 2020 at 11:18 AM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, Aug 25, 2020 at 6:28 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> > Enable PCIe Controller and set PCIe bus clock frequency.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > Reviewed-by: Chris Paterson <Chris.Paterson2@...esas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
> i.e. will queue in renesas-devel for v5.10.
>
> One thing to double-check below.
>
> > --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
> > +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
> > @@ -238,6 +238,18 @@
> >         /* status = "okay"; */
> >  };
> >
> > +&pcie_bus_clk {
> > +       clock-frequency = <100000000>;
> > +};
> > +
> > +&pciec {
> > +       /* SW2[6] determines which connector is activated
> > +        * ON = PCIe X4 (connector-J7)
> > +        * OFF = mini-PCIe (connector-J26)
>
> The table on page 14 says it's the other way around.
>
> According to the CBTL02042ABQ datasheet, PCIe_SEL = low
> selects the first channel (PCIe x4), while PCIe_SEL = high selects the
> second channel (mini-PCIe).
> Enabling the switch ties the signal low, so the table must be wrong.
>
Referring to [1] page 3:

SEL = LOW: A↔B
SEL = HIGH: A↔C

And as per the schematic iW-PREJD-CS-01-R2.0-REL1.5.pdf channel B is
J7 (PCIe X 4) and channel C is J26 (mini PCIe slot).

Enabling the switch SW2[6] (ON) ties SEL to LOW -> channel B is J7 (PCIe X 4)
Disabling the switch SW2[6] (OFF) ties SEL to HIGH -> channel C is J26
(mini PCIe)

Also iW-PREJD-CS-01-R2.0-REL1.5.pdf page 14 (General purpose table DIP
Switch) mentions the above.

[1] https://www.mouser.co.uk/datasheet/2/302/CBTL02042A_CBTL02042B-1126164.pdf

Cheers,
Prabhakar

> > +        */
> > +       status = "okay";
> > +};
> > +
> >  &pfc {
> >         avb_pins: avb {
> >                 groups = "avb_mdio", "avb_gmii";
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds