linux-kernel - Re: [PATCH v3 2/6] perf tsc: Add rdtsc() for Arm64

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 3 Sep 2020 10:23:54 +0800
From:   Leo Yan <leo.yan@...aro.org>
To:     peterz@...radead.org
Cc:     Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Ingo Molnar <mingo@...hat.com>, Wei Li <liwei391@...wei.com>,
        Al Grant <al.grant@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>,
        Adrian Hunter <adrian.hunter@...el.com>,
        "Naveen N. Rao" <naveen.n.rao@...ux.vnet.ibm.com>,
        Nick Desaulniers <ndesaulniers@...gle.com>,
        Kemeng Shi <shikemeng@...wei.com>,
        Ian Rogers <irogers@...gle.com>,
        John Garry <john.garry@...wei.com>,
        Stephane Eranian <eranian@...gle.com>,
        Nick Gasson <nick.gasson@....com>,
        Andi Kleen <ak@...ux.intel.com>,
        Steve MacLean <Steve.MacLean@...rosoft.com>,
        "Gustavo A. R. Silva" <gustavoars@...nel.org>,
        Kan Liang <kan.liang@...ux.intel.com>,
        Will Deacon <will@...nel.org>,
        James Clark <james.clark@....com>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 2/6] perf tsc: Add rdtsc() for Arm64

Hi Peter,

On Wed, Sep 02, 2020 at 03:48:05PM +0200, Peter Zijlstra wrote:
> On Wed, Sep 02, 2020 at 02:21:27PM +0100, Leo Yan wrote:
> > The system register CNTVCT_EL0 can be used to retrieve the counter from
> > user space.  Add rdtsc() for Arm64.
> 
> > +u64 rdtsc(void)
> > +{
> > +	u64 val;
> 
> Would it make sense to put a comment in that this counter is/could-be
> 'short' ? Because unlike x86-TSC, this thing isn't architecturally
> specified to be 64bits wide.

Will add below comments:

According to ARM DDI 0487F.c, from Armv8.0 to Armv8.5 inclusive, the
system counter is at least 56 bits wide; from Armv8.6, the counter must
be 64 bits wide.  So the system counter could be less than 64 bits wide
and it is attributed with the flag 'cap_user_time_short' is true.

Thanks for reviewing,
Leo

> 
> > +	asm volatile("mrs %0, cntvct_el0" : "=r" (val));
> > +
> > +	return val;
> > +}
> > -- 
> > 2.17.1
> >