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Date: Fri, 4 Sep 2020 11:38:50 +0100 From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> To: Geert Uytterhoeven <geert+renesas@...der.be>, Marek Vasut <marek.vasut+renesas@...il.com>, Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>, Bjorn Helgaas <bhelgaas@...gle.com>, Rob Herring <robh+dt@...nel.org>, Magnus Damm <magnus.damm@...il.com>, Kishon Vijay Abraham I <kishon@...com>, Lorenzo Pieralisi <lorenzo.pieralisi@....com>, Arnd Bergmann <arnd@...db.de>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, linux-pci@...r.kernel.org, devicetree@...r.kernel.org Cc: linux-renesas-soc@...r.kernel.org, linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, Prabhakar <prabhakar.csengg@...il.com> Subject: [PATCH 2/3] arm64: dts: renesas: r8a774e1: Add PCIe EP nodes Add PCIe EP nodes for R8A774E1 Soc dtsi. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> Reviewed-by: Biju Das <biju.das.jz@...renesas.com> --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 38 +++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index e5445ba99e84..272df6022442 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2468,6 +2468,44 @@ status = "disabled"; }; + pciec0_ep: pcie-ep@...00000 { + compatible = "renesas,r8a774e1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xfe000000 0 0x80000>, + <0x0 0xfe100000 0 0x100000>, + <0x0 0xfe200000 0 0x200000>, + <0x0 0x30000000 0 0x8000000>, + <0x0 0x38000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>; + clock-names = "pcie"; + resets = <&cpg 319>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@...00000 { + compatible = "renesas,r8a774e1-pcie-ep", + "renesas,rcar-gen3-pcie-ep"; + reg = <0x0 0xee800000 0 0x80000>, + <0x0 0xee900000 0 0x100000>, + <0x0 0xeea00000 0 0x200000>, + <0x0 0xc0000000 0 0x8000000>, + <0x0 0xc8000000 0 0x8000000>; + reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>; + clock-names = "pcie"; + resets = <&cpg 318>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + status = "disabled"; + }; + vspbc: vsp@...20000 { compatible = "renesas,vsp2"; reg = <0 0xfe920000 0 0x8000>; -- 2.17.1
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