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Message-ID: <0bdd7132-cdbf-02eb-0078-ec644b6611ca@wanyeetech.com>
Date: Mon, 7 Sep 2020 01:09:45 +0800
From: Zhou Yanjie <zhouyanjie@...yeetech.com>
To: Paul Cercueil <paul@...pouillou.net>
Cc: linus.walleij@...aro.org, linux-gpio@...r.kernel.org,
linux-kernel@...r.kernel.org, aric.pzqi@...enic.com,
dongsheng.qiu@...enic.com, rick.tyliu@...enic.com,
yanfei.li@...enic.com, sernia.zhou@...mail.com,
zhenwenjin@...il.com
Subject: Re: [PATCH v2 1/3] pinctrl: Ingenic: Add SSI pins support for JZ4770
and JZ4780.
Hi Paul,
在 2020/9/6 下午10:17, Paul Cercueil 写道:
> Hi Zhou,
>
> Le ven. 4 sept. 2020 à 15:27, Paul Cercueil <paul@...pouillou.net> a
> écrit :
>> Hi Zhou,
>>
>> Le lun. 31 août 2020 à 23:43, 周琰杰 (Zhou Yanjie)
>> <zhouyanjie@...yeetech.com> a écrit :
>>> Add SSI pins support for the JZ4770 SoC and the
>>> JZ4780 SoC from Ingenic.
>>>
>>> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
>>> ---
>>>
>>> Notes:
>>> v1->v2:
>>> Rebase on top of kernel 5.9-rc3.
>>>
>>> drivers/pinctrl/pinctrl-ingenic.c | 267
>>> ++++++++++++++++++++++++++++++++++++++
>>> 1 file changed, 267 insertions(+)
>>>
>>> diff --git a/drivers/pinctrl/pinctrl-ingenic.c
>>> b/drivers/pinctrl/pinctrl-ingenic.c
>>> index a8d1b53ec4c1..00f29fd684fa 100644
>>> --- a/drivers/pinctrl/pinctrl-ingenic.c
>>> +++ b/drivers/pinctrl/pinctrl-ingenic.c
>>> @@ -633,6 +633,46 @@ static int jz4770_uart2_data_pins[] = { 0x5c,
>>> 0x5e, };
>>> static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
>>> static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
>>> static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
>>> +static int jz4770_ssi0_dt_a_pins[] = { 0x15, };
>>> +static int jz4770_ssi0_dt_b_pins[] = { 0x35, };
>>> +static int jz4770_ssi0_dt_d_pins[] = { 0x55, };
>>> +static int jz4770_ssi0_dt_e_pins[] = { 0x71, };
>>> +static int jz4770_ssi0_dr_a_pins[] = { 0x14, };
>>> +static int jz4770_ssi0_dr_b_pins[] = { 0x34, };
>>> +static int jz4770_ssi0_dr_d_pins[] = { 0x54, };
>>> +static int jz4770_ssi0_dr_e_pins[] = { 0x6e, };
>>> +static int jz4770_ssi0_clk_a_pins[] = { 0x12, };
>>> +static int jz4770_ssi0_clk_b_pins[] = { 0x3c, };
>>> +static int jz4770_ssi0_clk_d_pins[] = { 0x58, };
>>> +static int jz4770_ssi0_clk_e_pins[] = { 0x6f, };
>>> +static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, };
>>> +static int jz4770_ssi0_gpc_d_pins[] = { 0x56, };
>>> +static int jz4770_ssi0_gpc_e_pins[] = { 0x73, };
>>> +static int jz4770_ssi0_ce0_a_pins[] = { 0x13, };
>>> +static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, };
>>> +static int jz4770_ssi0_ce0_d_pins[] = { 0x59, };
>>> +static int jz4770_ssi0_ce0_e_pins[] = { 0x70, };
>>> +static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, };
>>> +static int jz4770_ssi0_ce1_d_pins[] = { 0x57, };
>>> +static int jz4770_ssi0_ce1_e_pins[] = { 0x72, };
>>> +static int jz4770_ssi1_dt_b_pins[] = { 0x35, };
>>> +static int jz4770_ssi1_dt_d_pins[] = { 0x55, };
>>> +static int jz4770_ssi1_dt_e_pins[] = { 0x71, };
>>> +static int jz4770_ssi1_dr_b_pins[] = { 0x34, };
>>> +static int jz4770_ssi1_dr_d_pins[] = { 0x54, };
>>> +static int jz4770_ssi1_dr_e_pins[] = { 0x6e, };
>>> +static int jz4770_ssi1_clk_b_pins[] = { 0x3c, };
>>> +static int jz4770_ssi1_clk_d_pins[] = { 0x58, };
>>> +static int jz4770_ssi1_clk_e_pins[] = { 0x6f, };
>>> +static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, };
>>> +static int jz4770_ssi1_gpc_d_pins[] = { 0x56, };
>>> +static int jz4770_ssi1_gpc_e_pins[] = { 0x73, };
>>> +static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, };
>>> +static int jz4770_ssi1_ce0_d_pins[] = { 0x59, };
>>> +static int jz4770_ssi1_ce0_e_pins[] = { 0x70, };
>>> +static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, };
>>> +static int jz4770_ssi1_ce1_d_pins[] = { 0x57, };
>>> +static int jz4770_ssi1_ce1_e_pins[] = { 0x72, };
>>> static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
>>> static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
>>> static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
>>> @@ -703,6 +743,46 @@ static int jz4770_uart2_data_funcs[] = { 0, 0, };
>>> static int jz4770_uart2_hwflow_funcs[] = { 0, 0, };
>>> static int jz4770_uart3_data_funcs[] = { 0, 1, };
>>> static int jz4770_uart3_hwflow_funcs[] = { 0, 0, };
>>> +static int jz4770_ssi0_dt_a_funcs[] = { 2, };
>>> +static int jz4770_ssi0_dt_b_funcs[] = { 1, };
>>> +static int jz4770_ssi0_dt_d_funcs[] = { 1, };
>>> +static int jz4770_ssi0_dt_e_funcs[] = { 0, };
>>> +static int jz4770_ssi0_dr_a_funcs[] = { 1, };
>>> +static int jz4770_ssi0_dr_b_funcs[] = { 1, };
>>> +static int jz4770_ssi0_dr_d_funcs[] = { 1, };
>>> +static int jz4770_ssi0_dr_e_funcs[] = { 0, };
>>> +static int jz4770_ssi0_clk_a_funcs[] = { 2, };
>>> +static int jz4770_ssi0_clk_b_funcs[] = { 1, };
>>> +static int jz4770_ssi0_clk_d_funcs[] = { 1, };
>>> +static int jz4770_ssi0_clk_e_funcs[] = { 0, };
>>> +static int jz4770_ssi0_gpc_b_funcs[] = { 1, };
>>> +static int jz4770_ssi0_gpc_d_funcs[] = { 1, };
>>> +static int jz4770_ssi0_gpc_e_funcs[] = { 0, };
>>> +static int jz4770_ssi0_ce0_a_funcs[] = { 2, };
>>> +static int jz4770_ssi0_ce0_b_funcs[] = { 1, };
>>> +static int jz4770_ssi0_ce0_d_funcs[] = { 1, };
>>> +static int jz4770_ssi0_ce0_e_funcs[] = { 0, };
>>> +static int jz4770_ssi0_ce1_b_funcs[] = { 1, };
>>> +static int jz4770_ssi0_ce1_d_funcs[] = { 1, };
>>> +static int jz4770_ssi0_ce1_e_funcs[] = { 0, };
>>> +static int jz4770_ssi1_dt_b_funcs[] = { 2, };
>>> +static int jz4770_ssi1_dt_d_funcs[] = { 2, };
>>> +static int jz4770_ssi1_dt_e_funcs[] = { 1, };
>>> +static int jz4770_ssi1_dr_b_funcs[] = { 2, };
>>> +static int jz4770_ssi1_dr_d_funcs[] = { 2, };
>>> +static int jz4770_ssi1_dr_e_funcs[] = { 1, };
>>> +static int jz4770_ssi1_clk_b_funcs[] = { 2, };
>>> +static int jz4770_ssi1_clk_d_funcs[] = { 2, };
>>> +static int jz4770_ssi1_clk_e_funcs[] = { 1, };
>>> +static int jz4770_ssi1_gpc_b_funcs[] = { 2, };
>>> +static int jz4770_ssi1_gpc_d_funcs[] = { 2, };
>>> +static int jz4770_ssi1_gpc_e_funcs[] = { 1, };
>>> +static int jz4770_ssi1_ce0_b_funcs[] = { 2, };
>>> +static int jz4770_ssi1_ce0_d_funcs[] = { 2, };
>>> +static int jz4770_ssi1_ce0_e_funcs[] = { 1, };
>>> +static int jz4770_ssi1_ce1_b_funcs[] = { 2, };
>>> +static int jz4770_ssi1_ce1_d_funcs[] = { 2, };
>>> +static int jz4770_ssi1_ce1_e_funcs[] = { 1, };
>>> static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
>>> static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, };
>>> static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, };
>>> @@ -763,6 +843,46 @@ static const struct group_desc jz4770_groups[]
>>> = {
>>> INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow),
>>> INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data),
>>> INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow),
>>> + INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a),
>>> + INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b),
>>> + INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d),
>>> + INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e),
>>> + INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a),
>>> + INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b),
>>> + INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d),
>>> + INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e),
>>
>> The common acronyms associated with SPI are MISO / MOSI, I think it
>> would make sense to use them instead of DR / DT. What do you think?
>
> Just noticed that the X1000 has already SPI pins named DR / DT, so
> disregard my comment, it's better to use the same name convention
> across the whole file.
>
If necessary, I can send a patch to replace the dt/dr in X1000 and
X1830. What is your opinion?
Thanks and best regards!
> So:
> Reviewed-by: Paul Cercueil <paul@...pouillou.net>
>
> Cheers,
> -Paul
>
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