linux-kernel - Re: [PATCH 0/2] PCI: dwc: Add support to handle prefetchable memory separately

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 7 Sep 2020 18:10:06 +0100
From:   Lorenzo Pieralisi <lorenzo.pieralisi@....com>
To:     Vidya Sagar <vidyas@...dia.com>
Cc:     Gustavo Pimentel <Gustavo.Pimentel@...opsys.com>,
        "jingoohan1@...il.com" <jingoohan1@...il.com>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "amurray@...goodpenguin.co.uk" <amurray@...goodpenguin.co.uk>,
        "robh@...nel.org" <robh@...nel.org>,
        "thierry.reding@...il.com" <thierry.reding@...il.com>,
        "jonathanh@...dia.com" <jonathanh@...dia.com>,
        alan.mikhak@...ive.com, kishon@...com,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "kthota@...dia.com" <kthota@...dia.com>,
        "mmaddireddy@...dia.com" <mmaddireddy@...dia.com>,
        "sagar.tv@...il.com" <sagar.tv@...il.com>
Subject: Re: [PATCH 0/2] PCI: dwc: Add support to handle prefetchable memory
 separately

On Mon, Jul 06, 2020 at 10:05:06AM +0530, Vidya Sagar wrote:
> 
> 
> On 18-Jun-20 12:26 AM, Vidya Sagar wrote:
> > 
> > 
> > On 02-Jun-20 10:37 PM, Gustavo Pimentel wrote:
> > > External email: Use caution opening links or attachments
> > > 
> > > 
> > > On Tue, Jun 2, 2020 at 11:9:38, Vidya Sagar <vidyas@...dia.com> wrote:
> > > 
> > > > In this patch series,
> > > > Patch-1
> > > > adds required infrastructure to deal with prefetchable memory region
> > > > information coming from 'ranges' property of the respective
> > > > device-tree node
> > > > separately from non-prefetchable memory region information.
> > > > Patch-2
> > > > Adds support to use ATU region-3 for establishing the mapping
> > > > between CPU
> > > > addresses and PCIe bus addresses.
> > > > It also changes the logic to determine whether mapping is
> > > > required or not by
> > > > checking both CPU address and PCIe bus address for both prefetchable and
> > > > non-prefetchable regions. If the addresses are same, then, it is
> > > > understood
> > > > that 1:1 mapping is in place and there is no need to setup ATU mapping
> > > > whereas if the addresses are not the same, then, there is a need
> > > > to setup ATU
> > > > mapping. This is certainly true for Tegra194 and what I heard
> > > > from our HW
> > > > engineers is that it should generally be true for any DWC based
> > > > implementation
> > > > also.
> > > > Hence, I request Synopsys folks (Jingoo Han & Gustavo Pimentel
> > > > ??) to confirm
> > > > the same so that this particular patch won't cause any
> > > > regressions for other
> > > > DWC based platforms.
> > > 
> > > Hi Vidya,
> > > 
> > > Unfortunately due to the COVID-19 lockdown, I can't access my development
> > > prototype setup to test your patch.
> > > It might take some while until I get the possibility to get access to it
> > > again.
> > Hi Gustavo,
> > Did you find time to check this?
> > Adding Kishon and Alan as well to take a look at this and verify on
> > their platforms if possible.
> Hi Kishon and Alan, did you find time to verify this on your respective
> platforms?

Yes please. I would like to merge this code, in preparation for that
to happen mind rebasing the series against my pci/dwc branch with
Rob's suggested changes implemented ?

Thanks a lot,
Lorenzo