lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Mon, 7 Sep 2020 13:11:09 +0200
From:   Borislav Petkov <bp@...en8.de>
To:     "Jason A. Donenfeld" <Jason@...c4.com>
Cc:     Srinivas Pandruvada <srinivas.pandruvada@...ux.intel.com>,
        kitsunyan <kitsunyan@...mail.cc>, X86 ML <x86@...nel.org>,
        LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] x86/msr: do not warn on writes to OC_MAILBOX

Hi,

On Mon, Sep 07, 2020 at 12:46:35PM +0200, Jason A. Donenfeld wrote:
> Are you sure that intel-undervolt using OC_MAILBOX from userspace is
> actually a "misuse"? Should the kernel or kernel drivers actually be
> involved with the task of underclocking? This seems pretty squarely in
> the realm of "hobbyists poking and prodding at their CPUs" rather than
> something made for a kernel driver, right?

The only thing I'm sure is that *if* it makes sense for any driver to
control something in the hardware over MSRs, it should *not* poke at
naked MSRs but use a proper interface.

I'd leave it to the people who actually need this interface, to explain
why they do.

> Also, what was the justification for whitelisting
> MSR_IA32_ENERGY_PERF_BIAS?

That's:

tools/power/x86/x86_energy_perf_policy/x86_energy_perf_policy.c

Once that thing gets converted to a proper interface too, that MSR goes
off the allowlist too.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Powered by blists - more mailing lists