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Message-ID: <010101746c377537-ce93e925-598b-4dce-bb16-4cda020f4d6f-000000@us-west-2.amazonses.com>
Date: Tue, 8 Sep 2020 05:36:48 +0000
From: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
To: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Douglas Anderson <dianders@...omium.org>
Cc: Stephen Boyd <swboyd@...omium.org>, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org,
"Isaac J. Manjarres" <isaacm@...eaurora.org>,
Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
Subject: [PATCHv3] soc: qcom: llcc: Support chipsets that can write to llcc registers
From: "Isaac J. Manjarres" <isaacm@...eaurora.org>
Older chipsets may not be allowed to configure certain LLCC registers
as that is handled by the secure side software. However, this is not
the case for newer chipsets and they must configure these registers
according to the contents of the SCT table, while keeping in mind that
older targets may not have these capabilities. So add support to allow
such configuration of registers to enable capacity based allocation
and power collapse retention for capable chipsets.
Reason for choosing capacity based allocation rather than the default
way based allocation is because capacity based allocation allows more
finer grain partition and provides more flexibility in configuration.
As for the retention through power collapse, it has an advantage where
the cache hits are more when we wake up from power collapse although
it does burn more power but the exact power numbers are not known at
the moment.
Signed-off-by: Isaac J. Manjarres <isaacm@...eaurora.org>
(sai: use existing config instead of dt property and commit msg change)
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@...eaurora.org>
---
Changes in v3:
* Drop separate table and use existing qcom_llcc_config (Doug)
* More descriptive commit msg (Doug)
* Directly set the config instead of '|=' (Doug)
Changes in v2:
* Fix build errors reported by kernel test robot.
---
drivers/soc/qcom/llcc-qcom.c | 23 +++++++++++++++++++++++
include/linux/soc/qcom/llcc-qcom.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
index 429b5a60a1ba..b908656ce519 100644
--- a/drivers/soc/qcom/llcc-qcom.c
+++ b/drivers/soc/qcom/llcc-qcom.c
@@ -45,6 +45,9 @@
#define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
#define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
+#define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21F00
+#define LLCC_TRP_PCB_ACT 0x21F04
+
#define BANK_OFFSET_STRIDE 0x80000
/**
@@ -89,6 +92,7 @@ struct llcc_slice_config {
struct qcom_llcc_config {
const struct llcc_slice_config *sct_data;
int size;
+ bool need_llcc_cfg;
};
static const struct llcc_slice_config sc7180_data[] = {
@@ -122,11 +126,13 @@ static const struct llcc_slice_config sdm845_data[] = {
static const struct qcom_llcc_config sc7180_cfg = {
.sct_data = sc7180_data,
.size = ARRAY_SIZE(sc7180_data),
+ .need_llcc_cfg = true,
};
static const struct qcom_llcc_config sdm845_cfg = {
.sct_data = sdm845_data,
.size = ARRAY_SIZE(sdm845_data),
+ .need_llcc_cfg = false,
};
static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER;
@@ -327,6 +333,7 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
u32 attr0_val;
u32 max_cap_cacheline;
u32 sz;
+ u32 disable_cap_alloc, retain_pc;
int ret = 0;
const struct llcc_slice_config *llcc_table;
struct llcc_slice_desc desc;
@@ -369,6 +376,21 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
attr0_val);
if (ret)
return ret;
+
+ if (drv_data->need_llcc_config) {
+ disable_cap_alloc = llcc_table[i].dis_cap_alloc << llcc_table[i].slice_id;
+ ret = regmap_write(drv_data->bcast_regmap,
+ LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc);
+ if (ret)
+ return ret;
+
+ retain_pc = llcc_table[i].retain_on_pc << llcc_table[i].slice_id;
+ ret = regmap_write(drv_data->bcast_regmap,
+ LLCC_TRP_PCB_ACT, retain_pc);
+ if (ret)
+ return ret;
+ }
+
if (llcc_table[i].activate_on_init) {
desc.slice_id = llcc_table[i].slice_id;
ret = llcc_slice_activate(&desc);
@@ -474,6 +496,7 @@ static int qcom_llcc_probe(struct platform_device *pdev)
drv_data->cfg = llcc_cfg;
drv_data->cfg_size = sz;
+ drv_data->need_llcc_config = cfg->need_llcc_cfg;
mutex_init(&drv_data->lock);
platform_set_drvdata(pdev, drv_data);
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 90b864655822..52c780085f61 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -73,6 +73,7 @@ struct llcc_edac_reg_data {
* @bitmap: Bit map to track the active slice ids
* @offsets: Pointer to the bank offsets array
* @ecc_irq: interrupt for llcc cache error detection and reporting
+ * @need_llcc_config: check if llcc configuration is required
*/
struct llcc_drv_data {
struct regmap *regmap;
@@ -85,6 +86,7 @@ struct llcc_drv_data {
unsigned long *bitmap;
u32 *offsets;
int ecc_irq;
+ bool need_llcc_config;
};
#if IS_ENABLED(CONFIG_QCOM_LLCC)
--
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