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Message-Id: <20200908075716.30357-7-manivannan.sadhasivam@linaro.org>
Date: Tue, 8 Sep 2020 13:27:15 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: rjw@...ysocki.net, viresh.kumar@...aro.org, robh+dt@...nel.org,
agross@...nel.org, bjorn.andersson@...aro.org
Cc: amitk@...nel.org, linux-pm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-msm@...r.kernel.org, dmitry.baryshkov@...aro.org,
tdas@...eaurora.org,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Subject: [PATCH 6/7] cpufreq: qcom-hw: Add cpufreq support for SM8250 SoC
SM8250 SoC uses EPSS block for carrying out the cpufreq duties. Hence, add
support for it in the driver with relevant of_match data.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
---
drivers/cpufreq/qcom-cpufreq-hw.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c
index de816bcafd33..c3c397cc3dc6 100644
--- a/drivers/cpufreq/qcom-cpufreq-hw.c
+++ b/drivers/cpufreq/qcom-cpufreq-hw.c
@@ -285,8 +285,17 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = {
.lut_row_size = 32,
};
+static const struct qcom_cpufreq_soc_data sm8250_soc_data = {
+ .reg_enable = 0x0,
+ .reg_freq_lut = 0x100,
+ .reg_volt_lut = 0x200,
+ .reg_perf_state = 0x320,
+ .lut_row_size = 4,
+};
+
static const struct of_device_id qcom_cpufreq_hw_match[] = {
{ .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
+ { .compatible = "qcom,sm8250-epss", .data = &sm8250_soc_data },
{}
};
MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
--
2.17.1
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