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Message-ID: <CAHLCerNaf6hdC5etZoiq2pvvRt85CpD0yEW5_pcfpQKDjHk5Fw@mail.gmail.com>
Date: Tue, 8 Sep 2020 17:40:00 +0530
From: Amit Kucheria <amitk@...nel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Cc: "Rafael J. Wysocki" <rjw@...ysocki.net>,
Viresh Kumar <viresh.kumar@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Linux PM list <linux-pm@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>, LKML <linux-kernel@...r.kernel.org>,
linux-arm-msm <linux-arm-msm@...r.kernel.org>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Taniya Das <tdas@...eaurora.org>
Subject: Re: [PATCH 6/7] cpufreq: qcom-hw: Add cpufreq support for SM8250 SoC
On Tue, Sep 8, 2020 at 1:27 PM Manivannan Sadhasivam
<manivannan.sadhasivam@...aro.org> wrote:
>
> SM8250 SoC uses EPSS block for carrying out the cpufreq duties. Hence, add
> support for it in the driver with relevant of_match data.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Reviewed-by: Amit Kucheria <amitk@...nel.org>
> ---
> drivers/cpufreq/qcom-cpufreq-hw.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c
> index de816bcafd33..c3c397cc3dc6 100644
> --- a/drivers/cpufreq/qcom-cpufreq-hw.c
> +++ b/drivers/cpufreq/qcom-cpufreq-hw.c
> @@ -285,8 +285,17 @@ static const struct qcom_cpufreq_soc_data qcom_soc_data = {
> .lut_row_size = 32,
> };
>
> +static const struct qcom_cpufreq_soc_data sm8250_soc_data = {
> + .reg_enable = 0x0,
> + .reg_freq_lut = 0x100,
> + .reg_volt_lut = 0x200,
> + .reg_perf_state = 0x320,
> + .lut_row_size = 4,
> +};
> +
> static const struct of_device_id qcom_cpufreq_hw_match[] = {
> { .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
> + { .compatible = "qcom,sm8250-epss", .data = &sm8250_soc_data },
> {}
> };
> MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
> --
> 2.17.1
>
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