linux-kernel - [PATCH 0/6] clocksource: sp804: add support for Hisilicon sp804 timer

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Message-ID: <20200910031419.2790-1-thunder.leizhen@huawei.com>
Date:   Thu, 10 Sep 2020 11:14:13 +0800
From:   Zhen Lei <thunder.leizhen@...wei.com>
To:     Daniel Lezcano <daniel.lezcano@...aro.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        linux-kernel <linux-kernel@...r.kernel.org>
CC:     Zhen Lei <thunder.leizhen@...wei.com>,
        Libin <huawei.libin@...wei.com>,
        Kefeng Wang <wangkefeng.wang@...wei.com>,
        Jianguo Chen <chenjianguo3@...wei.com>
Subject: [PATCH 0/6] clocksource: sp804: add support for Hisilicon sp804 timer

The ARM SP804 supports a maximum of 32-bit counter, but Hisilicon extends
it to 64-bit. That means, the registers: TimerXload, TimerXValue and
TimerXBGLoad are 64bits, all other registers are the same as those in the
SP804. The driver code can be completely reused except that the register
offset is different

The register offset differences between ARM-SP804 and HISI-SP804 are as follows:

	ARM-SP804			HISI-SP804
TIMER_LOAD      0x00		HISI_TIMER_LOAD         0x00
				HISI_TIMER_LOAD_H       0x04
TIMER_VALUE     0x04		HISI_TIMER_VALUE        0x08
				HISI_TIMER_VALUE_H      0x0c
TIMER_CTRL      0x08		HISI_TIMER_CTRL         0x10
TIMER_INTCLR    0x0c		HISI_TIMER_INTCLR       0x14
TIMER_RIS       0x10		HISI_TIMER_RIS          0x18
TIMER_MIS       0x14		HISI_TIMER_MIS          0x1c
TIMER_BGLOAD    0x18		HISI_TIMER_BGLOAD       0x20
				HISI_TIMER_BGLOAD_H     0x24
TIMER_2_BASE    0x20		HISI_TIMER_2_BASE       0x40
----------------

In order to make the timer-sp804 driver support both ARM-SP804 and HISI-SP804.
Create a new structure "sp804_clkevt" to record the calculated registers
address in advance, avoid judging and calculating the register address every
place that is used.

For example:
	struct sp804_timer arm_sp804_timer = {
		.ctrl	= TIMER_CTRL,
	};

	struct sp804_timer hisi_sp804_timer = {
		.ctrl	= HISI_TIMER_CTRL,
	};

	struct sp804_clkevt clkevt;

In the initialization phase:
	if (hisi_sp804)
		clkevt.ctrl = base + hisi_sp804_timer.ctrl;
	else if (arm_sp804)
		clkevt.ctrl = base + arm_sp804_timer.ctrl;

After initialization:
-	writel(0, base + TIMER_CTRL);
+	writel(0, clkevt.ctrl);
----------------

Additional information:
These patch series are the V2 of https://lore.kernel.org/patchwork/cover/681876/
And many of the main ideas in https://lore.kernel.org/patchwork/patch/681875/ have been considered.
Thanks for Daniel Lezcano's review comments.


Kefeng Wang (1):
  clocksource: sp804: cleanup clk_get_sys()

Zhen Lei (5):
  clocksource: sp804: remove unused sp804_timer_disable() and
    timer-sp804.h
  clocksource: sp804: prepare for support non-standard register offset
  clocksource: sp804: support non-standard register offset
  clocksource: sp804: add support for Hisilicon sp804 timer
  clocksource: sp804: enable Hisilicon sp804 timer 64bit mode

 drivers/clocksource/timer-sp.h    |  47 ++++++++
 drivers/clocksource/timer-sp804.c | 194 ++++++++++++++++++++----------
 include/clocksource/timer-sp804.h |  29 -----
 3 files changed, 178 insertions(+), 92 deletions(-)
 delete mode 100644 include/clocksource/timer-sp804.h

-- 
2.26.0.106.g9fadedd