linux-kernel - Re: [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype

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Message-ID: <CAJMQK-g+pPR6ZrSJHPPcR9Tqw_4QjuMyUqML-RoPOjfnYZ=YGA@mail.gmail.com>
Date:   Thu, 10 Sep 2020 21:40:59 +0800
From:   Hsin-Yi Wang <hsinyi@...omium.org>
To:     Matthias Brugger <matthias.bgg@...il.com>
Cc:     "moderated list:ARM/Mediatek SoC support" 
        <linux-mediatek@...ts.infradead.org>,
        Rob Herring <robh+dt@...nel.org>,
        Devicetree List <devicetree@...r.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        lkml <linux-kernel@...r.kernel.org>,
        Enric Balletbo i Serra <enric.balletbo@...labora.com>,
        Eddie Huang <eddie.huang@...iatek.com>
Subject: Re: [PATCH v2 1/2] arm64: dts: mt8173: Set uart to mmio32 iotype

On Thu, Sep 10, 2020 at 6:25 PM Matthias Brugger <matthias.bgg@...il.com> wrote:
>
> Hi,
>
> On 10/09/2020 10:43, Hsin-Yi Wang wrote:
> > Set uart iotype to mmio32 to make earlycon work with stdout-path.
> >
> > Signed-off-by: Hsin-Yi Wang <hsinyi@...omium.org>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++++++
> >   1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > index 5e046f9d48ce9..ca6ea71f5f435 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> > @@ -613,6 +613,8 @@ uart0: serial@...02000 {
> >                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
>
> Why do we need that, we have
> device->port.iotype = UPIO_MEM32;
> in early_mtk8250_setup(). That should do the job already.
>
>

But if we don't change in dts, we would see
[    0.000000] earlycon: mtk8250 at MMIO 0x0000000011002000 (options '115200n8')
instead of
[    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options
'115200n8')

Perhaps we should move the pr_info part in earlycon_init() after
match->setup(). Since setup may change iotype. What do you think?


> > +                     reg-shift = <2>;
>
> Can't we just add
> device->port.regshift = 2;
> to early_mtk8250_setup()? I think that would be a cleaner solution. As the
> serial device is the same for all SoCs, I don't expect any regression here.
>
> CCing Eddie to correct me, if I'm wrong :)
>
> Regards,
> Matthias
>
> >                       status = "disabled";
> >               };
> >
> > @@ -623,6 +625,8 @@ uart1: serial@...03000 {
> >                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> >                       status = "disabled";
> >               };
> >
> > @@ -633,6 +637,8 @@ uart2: serial@...04000 {
> >                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> >                       status = "disabled";
> >               };
> >
> > @@ -643,6 +649,8 @@ uart3: serial@...05000 {
> >                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
> >                       clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
> >                       clock-names = "baud", "bus";
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> >                       status = "disabled";
> >               };
> >
> >