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Message-Id: <fe2a6ead3028f14b3b20c2340078e784bb8072c5.1599719352.git.greentime.hu@sifive.com>
Date: Thu, 10 Sep 2020 16:12:06 +0800
From: Greentime Hu <greentime.hu@...ive.com>
To: greentime.hu@...ive.com, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, aou@...s.berkeley.edu,
palmer@...belt.com, paul.walmsley@...ive.com
Cc: Guo Ren <guoren@...ux.alibaba.com>
Subject: [RFC PATCH v7 11/21] riscv: Add ptrace vector support
This patch adds ptrace support for riscv vector. The vector registers will
be saved in datap pointer of __riscv_v_state. This pointer will be set
right after the __riscv_v_state data structure then it will be put in ubuf
for ptrace system call to get or set. It will check if the datap got from
ubuf is set to the correct address or not when the ptrace system call is
trying to set the vector registers.
[guoren@...ux.alibaba.com: Add the first version porting to support vector
of ptrace]
Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
---
arch/riscv/include/uapi/asm/ptrace.h | 18 +++++++
arch/riscv/kernel/ptrace.c | 74 ++++++++++++++++++++++++++++
include/uapi/linux/elf.h | 1 +
3 files changed, 93 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/ptrace.h b/arch/riscv/include/uapi/asm/ptrace.h
index 661b0466b850..42144fe6acee 100644
--- a/arch/riscv/include/uapi/asm/ptrace.h
+++ b/arch/riscv/include/uapi/asm/ptrace.h
@@ -80,16 +80,34 @@ union __riscv_fp_state {
struct __riscv_v_state {
__u32 magic;
__u32 size;
+ /*
+ * This is the size of vector registers not including
+ * __riscv_v_state itself.
+ */
unsigned long vstart;
unsigned long vl;
unsigned long vtype;
unsigned long vcsr;
void *datap;
+ /*
+ * In signal handler, datap will be set a correct user stack offset
+ * and vector registers will be copied to the address of datap
+ * pointer.
+ *
+ * In ptrace syscall, datap will be set to zero and the vector
+ * registers will be copied to the address right after this
+ * structure.
+ */
#if __riscv_xlen == 32
__u32 __padding;
#endif
} __attribute__((aligned(16)));
+/*
+ * To define a practical maximum vlenb for ptrace and it may need to be
+ * extended someday.
+ */
+#define RISCV_MAX_VLENB (16384)
#endif /* __ASSEMBLY__ */
#endif /* _UAPI_ASM_RISCV_PTRACE_H */
diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c
index 2d6395f5ad54..c5f96b4e3df9 100644
--- a/arch/riscv/kernel/ptrace.c
+++ b/arch/riscv/kernel/ptrace.c
@@ -10,6 +10,7 @@
#include <asm/ptrace.h>
#include <asm/syscall.h>
#include <asm/thread_info.h>
+#include <asm/switch_to.h>
#include <linux/audit.h>
#include <linux/ptrace.h>
#include <linux/elf.h>
@@ -26,6 +27,9 @@ enum riscv_regset {
#ifdef CONFIG_FPU
REGSET_F,
#endif
+#ifdef CONFIG_VECTOR
+ REGSET_V,
+#endif
};
static int riscv_gpr_get(struct task_struct *target,
@@ -81,6 +85,66 @@ static int riscv_fpr_set(struct task_struct *target,
}
#endif
+#ifdef CONFIG_VECTOR
+static int riscv_vr_get(struct task_struct *target,
+ const struct user_regset *regset,
+ struct membuf to)
+{
+ struct __riscv_v_state *vstate = &target->thread.vstate;
+ __u32 magic = RVV_MAGIC;
+
+ /* Copy magic number */
+ membuf_store(&to, magic);
+ /* Copy vector header from vstate. */
+ membuf_write(&to, &(vstate->size), RISCV_V_STATE_DATAP - RISCV_V_STATE_SIZE);
+ membuf_zero(&to, sizeof(void *));
+#if __riscv_xlen == 32
+ membuf_zero(&to, sizeof(__u32));
+#endif
+ /* Copy all the vector registers from vstate. */
+ return membuf_write(&to, vstate->datap, vstate->size);
+}
+
+static int riscv_vr_set(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ const void *kbuf, const void __user *ubuf)
+{
+ int ret, size;
+ struct __riscv_v_state *vstate = &target->thread.vstate;
+
+ /* Skip copy magic because kernel doesn't need to use it. */
+ size = sizeof(vstate->magic);
+ pos += size;
+ count -= size;
+ ubuf += size;
+
+ /* Copy rest of the vstate except datap and __padding. */
+ ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate, 0,
+ RISCV_V_STATE_DATAP);
+ if (unlikely(ret))
+ return ret;
+
+ /* Skip copy datap. */
+ size = sizeof(vstate->datap);
+ count -= size;
+ ubuf += size;
+
+#if __riscv_xlen == 32
+ /* Skip copy _padding. */
+ size = sizeof(vstate->__padding);
+ count -= size;
+ ubuf += size;
+#endif
+
+ /* Copy all the vector registers. */
+ pos = 0;
+ ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, vstate->datap,
+ 0, vstate->size);
+ return ret;
+}
+#endif
+
static const struct user_regset riscv_user_regset[] = {
[REGSET_X] = {
.core_note_type = NT_PRSTATUS,
@@ -100,6 +164,16 @@ static const struct user_regset riscv_user_regset[] = {
.set = riscv_fpr_set,
},
#endif
+#ifdef CONFIG_VECTOR
+ [REGSET_V] = {
+ .core_note_type = NT_RISCV_VECTOR,
+ .align = 16,
+ .n = (32 * RISCV_MAX_VLENB)/sizeof(__u32),
+ .size = sizeof(__u32),
+ .regset_get = riscv_vr_get,
+ .set = riscv_vr_set,
+ },
+#endif
};
static const struct user_regset_view riscv_user_native_view = {
diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index 22220945a5fd..66d02df08f46 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -430,6 +430,7 @@ typedef struct elf64_shdr {
#define NT_MIPS_DSP 0x800 /* MIPS DSP ASE registers */
#define NT_MIPS_FP_MODE 0x801 /* MIPS floating-point mode */
#define NT_MIPS_MSA 0x802 /* MIPS SIMD registers */
+#define NT_RISCV_VECTOR 0x900 /* RISC-V vector registers */
/* Note types with note name "GNU" */
#define NT_GNU_PROPERTY_TYPE_0 5
--
2.28.0
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