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Message-Id: <3e0097c59860fbaa90aadc69d302fcc2e4ab351e.1599719352.git.greentime.hu@sifive.com>
Date:   Thu, 10 Sep 2020 16:12:12 +0800
From:   Greentime Hu <greentime.hu@...ive.com>
To:     greentime.hu@...ive.com, linux-riscv@...ts.infradead.org,
        linux-kernel@...r.kernel.org, aou@...s.berkeley.edu,
        palmer@...belt.com, paul.walmsley@...ive.com
Cc:     Han-Kuan Chen <hankuan.chen@...ive.com>
Subject: [RFC PATCH v7 17/21] riscv: Initialize vector registers with proper vsetvli then it can work normally

It may cause an illegal instruction exception if it doesn't use vsetvli
before vmv.v.i v0, 0.

Signed-off-by: Han-Kuan Chen <hankuan.chen@...ive.com>
Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
---
 arch/riscv/kernel/head.S | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index e97c7915ae27..74f2fd8430e0 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -375,6 +375,7 @@ ENTRY(reset_regs)
 
 	li	t1, SR_VS
 	csrs	CSR_STATUS, t1
+	vsetvli t1, x0, e8, m1
 	vmv.v.i v0, 0
 	vmv.v.i v1, 0
 	vmv.v.i v2, 0
-- 
2.28.0

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