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Message-Id: <1599734644-4791-2-git-send-email-sagar.kadam@sifive.com>
Date: Thu, 10 Sep 2020 16:14:02 +0530
From: Sagar Kadam <sagar.kadam@...ive.com>
To: linux-pwm@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-clk@...r.kernel.org
Cc: mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
paul.walmsley@...ive.com, palmer@...belt.com, tglx@...utronix.de,
jason@...edaemon.net, maz@...nel.org, thierry.reding@...il.com,
u.kleine-koenig@...gutronix.de, lee.jones@...aro.org,
aou@...s.berkeley.edu, yash.shah@...ive.com,
Sagar Kadam <sagar.kadam@...ive.com>
Subject: [PATCH v1 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema
FU540-C000 SoC from SiFive has a PRCI block, here we convert
the device tree bindings from txt to YAML.
Signed-off-by: Sagar Kadam <sagar.kadam@...ive.com>
---
.../bindings/clock/sifive/fu540-prci.txt | 46 -------------
.../bindings/clock/sifive/fu540-prci.yaml | 75 ++++++++++++++++++++++
2 files changed, 75 insertions(+), 46 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt
create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt
deleted file mode 100644
index 349808f..0000000
--- a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-SiFive FU540 PRCI bindings
-
-On the FU540 family of SoCs, most system-wide clock and reset integration
-is via the PRCI IP block.
-
-Required properties:
-- compatible: Should be "sifive,<chip>-prci". Only one value is
- supported: "sifive,fu540-c000-prci"
-- reg: Should describe the PRCI's register target physical address region
-- clocks: Should point to the hfclk device tree node and the rtcclk
- device tree node. The RTC clock here is not a time-of-day clock,
- but is instead a high-stability clock source for system timers
- and cycle counters.
-- #clock-cells: Should be <1>
-
-The clock consumer should specify the desired clock via the clock ID
-macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
-These macros begin with PRCI_CLK_.
-
-The hfclk and rtcclk nodes are required, and represent physical
-crystals or resonators located on the PCB. These nodes should be present
-underneath /, rather than /soc.
-
-Examples:
-
-/* under /, in PCB-specific DT data */
-hfclk: hfclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <33333333>;
- clock-output-names = "hfclk";
-};
-rtcclk: rtcclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <1000000>;
- clock-output-names = "rtcclk";
-};
-
-/* under /soc, in SoC-specific DT data */
-prci: clock-controller@...00000 {
- compatible = "sifive,fu540-c000-prci";
- reg = <0x0 0x10000000 0x0 0x1000>;
- clocks = <&hfclk>, <&rtcclk>;
- #clock-cells = <1>;
-};
diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
new file mode 100644
index 0000000..49386cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 SiFive, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
+
+maintainers:
+ - Sagar Kadam <sagar.kadam@...ive.com>
+ - Paul Walmsley <paul.walmsley@...ive.com>
+
+description:
+ On the FU540 family of SoCs, most system-wide clock and reset integration
+ is via the PRCI IP block.
+ The clock consumer should specify the desired clock via the clock ID
+ macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
+ These macros begin with PRCI_CLK_.
+
+ The hfclk and rtcclk nodes are required, and represent physical
+ crystals or resonators located on the PCB. These nodes should be present
+ underneath /, rather than /soc.
+
+properties:
+ compatible:
+ enum:
+ - sifive,fu540-c000-prci
+ description:
+ Should have "sifive,<soc>-prci", only one value is supported
+
+ reg:
+ maxItems: 1
+ description: Describe the PRCI's register target physical address region
+
+ clocks:
+ description:
+ Should point to the hfclk device tree node and the rtcclk device tree node.
+ The RTC clock here is not a time-of-day clock, but is instead a high-stability
+ clock source for system timers and cycle counters.
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ //hfclk and rtcclk present under /, in PCB-specific DT data
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <33333333>;
+ clock-output-names = "hfclk";
+ };
+ rtcclk: rtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1000000>;
+ clock-output-names = "rtcclk";
+ };
+
+ //under /soc, in SoC-specific DT data
+ prci: clock-controller@...00000 {
+ compatible = "sifive,fu540-c000-prci";
+ reg = <0x10000000 0x1000>;
+ clocks = <&hfclk>, <&rtcclk>;
+ #clock-cells = <1>;
+ };
--
2.7.4
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