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Message-ID: <20200910164751.GA501845@bogus>
Date: Thu, 10 Sep 2020 10:47:51 -0600
From: Rob Herring <robh@...nel.org>
To: Zhiqiang Hou <Zhiqiang.Hou@....com>
Cc: linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linuxppc-dev@...ts.ozlabs.org, bhelgaas@...gle.com,
lorenzo.pieralisi@....com, shawnguo@...nel.org, leoyang.li@....com,
kishon@...com, gustavo.pimentel@...opsys.com, roy.zang@....com,
jingoohan1@...il.com, andrew.murray@....com, mingkai.hu@....com,
minghuan.Lian@....com, Xiaowei Bao <xiaowei.bao@....com>
Subject: Re: [PATCHv7 10/12] arm64: dts: layerscape: Add PCIe EP node for
ls1088a
On Tue, Aug 11, 2020 at 05:54:39PM +0800, Zhiqiang Hou wrote:
> From: Xiaowei Bao <xiaowei.bao@....com>
>
> Add PCIe EP node for ls1088a to support EP mode.
>
> Signed-off-by: Xiaowei Bao <xiaowei.bao@....com>
> Reviewed-by: Andrew Murray <andrew.murray@....com>
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
> ---
> V7:
> - Rebase the patch without functionality change.
>
> .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 31 +++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> index 169f4742ae3b..915592141f1b 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> @@ -499,6 +499,17 @@
> status = "disabled";
> };
>
> + pcie_ep@...0000 {
pci-ep@...
> + compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
> + reg = <0x00 0x03400000 0x0 0x00100000
> + 0x20 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ib-windows = <24>;
> + num-ob-windows = <128>;
> + max-functions = /bits/ 8 <2>;
> + status = "disabled";
> + };
> +
> pcie@...0000 {
> compatible = "fsl,ls1088a-pcie";
> reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
> @@ -525,6 +536,16 @@
> status = "disabled";
> };
>
> + pcie_ep@...0000 {
> + compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
> + reg = <0x00 0x03500000 0x0 0x00100000
> + 0x28 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ib-windows = <6>;
> + num-ob-windows = <8>;
> + status = "disabled";
> + };
> +
> pcie@...0000 {
> compatible = "fsl,ls1088a-pcie";
> reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
> @@ -551,6 +572,16 @@
> status = "disabled";
> };
>
> + pcie_ep@...0000 {
> + compatible = "fsl,ls1088a-pcie-ep","fsl,ls-pcie-ep";
> + reg = <0x00 0x03600000 0x0 0x00100000
> + 0x30 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + num-ib-windows = <6>;
> + num-ob-windows = <8>;
> + status = "disabled";
> + };
> +
> smmu: iommu@...0000 {
> compatible = "arm,mmu-500";
> reg = <0 0x5000000 0 0x800000>;
> --
> 2.17.1
>
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