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Message-Id: <20200911192601.9591-5-krish.sadhukhan@oracle.com>
Date: Fri, 11 Sep 2020 19:26:01 +0000
From: Krish Sadhukhan <krish.sadhukhan@...cle.com>
To: kvm@...r.kernel.org
Cc: pbonzini@...hat.com, jmattson@...gle.com, tglx@...utronix.de,
mingo@...hat.com, bp@...en8.de, x86@...nel.org,
sean.j.christopherson@...el.com, vkuznets@...hat.com,
wanpengli@...cent.com, joro@...tes.org,
dave.hansen@...ux.intel.com, luto@...nel.org, peterz@...radead.org,
linux-kernel@...r.kernel.org, hpa@...or.com
Subject: [PATCH 4/4 v3] KVM: SVM: Don't flush cache if hardware enforces cache coherency across encryption domains
In some hardware implementations, coherency between the encrypted and
unencrypted mappings of the same physical page in a VM is enforced. In such a
system, it is not required for software to flush the VM's page from all CPU
caches in the system prior to changing the value of the C-bit for the page.
Signed-off-by: Krish Sadhukhan <krish.sadhukhan@...cle.com>
---
arch/x86/kvm/svm/sev.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index 402dc4234e39..8aa2209f2637 100644
--- a/arch/x86/kvm/svm/sev.c
+++ b/arch/x86/kvm/svm/sev.c
@@ -384,7 +384,8 @@ static void sev_clflush_pages(struct page *pages[], unsigned long npages)
uint8_t *page_virtual;
unsigned long i;
- if (npages == 0 || pages == NULL)
+ if (this_cpu_has(X86_FEATURE_HW_CACHE_COHERENCY) || npages == 0 ||
+ pages == NULL)
return;
for (i = 0; i < npages; i++) {
--
2.18.4
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