linux-kernel - Re: [PATCH 2/4 v3] x86: AMD: Add hardware-enforced cache coherency as a CPUID feature

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Message-ID: <c5cbc91e-f576-5cc7-a40c-c11abaea4ad2@intel.com>
Date:   Fri, 11 Sep 2020 12:36:12 -0700
From:   Dave Hansen <dave.hansen@...el.com>
To:     Krish Sadhukhan <krish.sadhukhan@...cle.com>, kvm@...r.kernel.org
Cc:     pbonzini@...hat.com, jmattson@...gle.com, tglx@...utronix.de,
        mingo@...hat.com, bp@...en8.de, x86@...nel.org,
        sean.j.christopherson@...el.com, vkuznets@...hat.com,
        wanpengli@...cent.com, joro@...tes.org,
        dave.hansen@...ux.intel.com, luto@...nel.org, peterz@...radead.org,
        linux-kernel@...r.kernel.org, hpa@...or.com
Subject: Re: [PATCH 2/4 v3] x86: AMD: Add hardware-enforced cache coherency as
 a CPUID feature

On 9/11/20 12:25 PM, Krish Sadhukhan wrote:
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 81335e6fe47d..0e5b27ee5931 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -293,6 +293,7 @@
>  #define X86_FEATURE_FENCE_SWAPGS_USER	(11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
>  #define X86_FEATURE_FENCE_SWAPGS_KERNEL	(11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
>  #define X86_FEATURE_SPLIT_LOCK_DETECT	(11*32+ 6) /* #AC for split lock */
> +#define X86_FEATURE_HW_CACHE_COHERENCY (11*32+ 7) /* AMD hardware-enforced cache coherency */

That's an awfully generic name.  We generally have "hardware-enforced
cache coherency" already everywhere. :)

This probably needs to say something about encryption, or even SEV
specifically.  I also don't see this bit in the "AMD64 Architecture
Programmer’s Manual".  Did I look in the wrong spot somehow?