linux-kernel - Re: [PATCH 2/4 v3] x86: AMD: Add hardware-enforced cache coherency as a CPUID feature

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Message-ID: <103bdf75-aa91-1c91-7727-e853b55a603c@intel.com>
Date:   Fri, 11 Sep 2020 13:58:29 -0700
From:   Dave Hansen <dave.hansen@...el.com>
To:     Krish Sadhukhan <krish.sadhukhan@...cle.com>, kvm@...r.kernel.org
Cc:     pbonzini@...hat.com, jmattson@...gle.com, tglx@...utronix.de,
        mingo@...hat.com, bp@...en8.de, x86@...nel.org,
        sean.j.christopherson@...el.com, vkuznets@...hat.com,
        wanpengli@...cent.com, joro@...tes.org,
        dave.hansen@...ux.intel.com, luto@...nel.org, peterz@...radead.org,
        linux-kernel@...r.kernel.org, hpa@...or.com
Subject: Re: [PATCH 2/4 v3] x86: AMD: Add hardware-enforced cache coherency as
 a CPUID feature

On 9/11/20 1:10 PM, Krish Sadhukhan wrote:
...
>>> +#define X86_FEATURE_HW_CACHE_COHERENCY (11*32+ 7) /* AMD
>>> hardware-enforced cache coherency */
>> That's an awfully generic name.  We generally have "hardware-enforced
>> cache coherency" already everywhere. :)
>>
>> This probably needs to say something about encryption, or even SEV
>> specifically.
> 
> How about X86_FEATURE_ENC_CACHE_COHERENCY ?

I think X86_FEATURE_SME_COHERENT would be the most appropriate name.
That bit, as defined, looks totally specific to SME.