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Message-ID: <c1eacedd-056d-d6a8-0407-2dea63f47bd9@amd.com>
Date: Fri, 11 Sep 2020 13:13:30 -0400
From: "Kazlauskas, Nicholas" <nicholas.kazlauskas@....com>
To: Rodrigo Siqueira <Rodrigo.Siqueira@....com>,
amd-gfx@...ts.freedesktop.org, dri-devel@...ts.freedesktop.org,
linux-kernel@...r.kernel.org
Cc: Harry Wentland <harry.wentland@....com>,
Leo Li <sunpeng.li@....com>,
Alex Deucher <alexander.deucher@....com>,
Christian König <christian.koenig@....com>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>, hersenxs.wu@....com
Subject: Re: [PATCH v2 1/4] drm/amd/display: Rework registers tracepoint
On 2020-09-11 10:59 a.m., Rodrigo Siqueira wrote:
> amdgpu_dc_rreg and amdgpu_dc_wreg are very similar, for this reason,
> this commits abstract these two events by using DECLARE_EVENT_CLASS and
> create an instance of it for each one of these events.
>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@....com>
This looks reasonable to me. Does this still show up as
amdpgu_dc_rrreg/amdgpu_dc_wreg in the captured trace log?
As long as we can still tell this apart you can consider this patch:
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@....com>
Regards,
Nicholas Kazlauskas
> ---
> .../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 55 ++++++++-----------
> 1 file changed, 24 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
> index d898981684d5..dd34e11b1079 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h
> @@ -31,40 +31,33 @@
>
> #include <linux/tracepoint.h>
>
> -TRACE_EVENT(amdgpu_dc_rreg,
> - TP_PROTO(unsigned long *read_count, uint32_t reg, uint32_t value),
> - TP_ARGS(read_count, reg, value),
> - TP_STRUCT__entry(
> - __field(uint32_t, reg)
> - __field(uint32_t, value)
> - ),
> - TP_fast_assign(
> - __entry->reg = reg;
> - __entry->value = value;
> - *read_count = *read_count + 1;
> - ),
> - TP_printk("reg=0x%08lx, value=0x%08lx",
> - (unsigned long)__entry->reg,
> - (unsigned long)__entry->value)
> -);
> +DECLARE_EVENT_CLASS(amdgpu_dc_reg_template,
> + TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
> + TP_ARGS(count, reg, value),
>
> -TRACE_EVENT(amdgpu_dc_wreg,
> - TP_PROTO(unsigned long *write_count, uint32_t reg, uint32_t value),
> - TP_ARGS(write_count, reg, value),
> - TP_STRUCT__entry(
> - __field(uint32_t, reg)
> - __field(uint32_t, value)
> - ),
> - TP_fast_assign(
> - __entry->reg = reg;
> - __entry->value = value;
> - *write_count = *write_count + 1;
> - ),
> - TP_printk("reg=0x%08lx, value=0x%08lx",
> - (unsigned long)__entry->reg,
> - (unsigned long)__entry->value)
> + TP_STRUCT__entry(
> + __field(uint32_t, reg)
> + __field(uint32_t, value)
> + ),
> +
> + TP_fast_assign(
> + __entry->reg = reg;
> + __entry->value = value;
> + *count = *count + 1;
> + ),
> +
> + TP_printk("reg=0x%08lx, value=0x%08lx",
> + (unsigned long)__entry->reg,
> + (unsigned long)__entry->value)
> );
>
> +DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_rreg,
> + TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
> + TP_ARGS(count, reg, value));
> +
> +DEFINE_EVENT(amdgpu_dc_reg_template, amdgpu_dc_wreg,
> + TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value),
> + TP_ARGS(count, reg, value));
>
> TRACE_EVENT(amdgpu_dc_performance,
> TP_PROTO(unsigned long read_count, unsigned long write_count,
>
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