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Date: Mon, 14 Sep 2020 12:00:00 -0600
From: Rob Herring <robh@...nel.org>
To: Sagar Kadam <sagar.kadam@...ive.com>
Cc: linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
devicetree@...r.kernel.org, paul.walmsley@...ive.com,
palmer@...belt.com, aou@...s.berkeley.edu, yash.shah@...ive.com
Subject: Re: [RESEND PATCH v2 1/1] dt-bindings: riscv: sifive-l2-cache:
convert bindings to json-schema
On Fri, Aug 28, 2020 at 10:25:43PM +0530, Sagar Kadam wrote:
> Convert the device tree bindings for the SiFive's FU540-C000 SoC's L2 Cache
> controller to YAML format.
>
> Signed-off-by: Sagar Kadam <sagar.kadam@...ive.com>
> ---
> .../devicetree/bindings/riscv/sifive-l2-cache.txt | 51 ------------
> .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 92 ++++++++++++++++++++++
> 2 files changed, 92 insertions(+), 51 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
> create mode 100644 Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
>
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
> deleted file mode 100644
> index 73d8f19..0000000
> --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.txt
> +++ /dev/null
> @@ -1,51 +0,0 @@
> -SiFive L2 Cache Controller
> ---------------------------
> -The SiFive Level 2 Cache Controller is used to provide access to fast copies
> -of memory for masters in a Core Complex. The Level 2 Cache Controller also
> -acts as directory-based coherency manager.
> -All the properties in ePAPR/DeviceTree specification applies for this platform
> -
> -Required Properties:
> ---------------------
> -- compatible: Should be "sifive,fu540-c000-ccache" and "cache"
> -
> -- cache-block-size: Specifies the block size in bytes of the cache.
> - Should be 64
> -
> -- cache-level: Should be set to 2 for a level 2 cache
> -
> -- cache-sets: Specifies the number of associativity sets of the cache.
> - Should be 1024
> -
> -- cache-size: Specifies the size in bytes of the cache. Should be 2097152
> -
> -- cache-unified: Specifies the cache is a unified cache
> -
> -- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals)
> -
> -- reg: Physical base address and size of L2 cache controller registers map
> -
> -Optional Properties:
> ---------------------
> -- next-level-cache: phandle to the next level cache if present.
> -
> -- memory-region: reference to the reserved-memory for the L2 Loosely Integrated
> - Memory region. The reserved memory node should be defined as per the bindings
> - in reserved-memory.txt
> -
> -
> -Example:
> -
> - cache-controller@...0000 {
> - compatible = "sifive,fu540-c000-ccache", "cache";
> - cache-block-size = <64>;
> - cache-level = <2>;
> - cache-sets = <1024>;
> - cache-size = <2097152>;
> - cache-unified;
> - interrupt-parent = <&plic0>;
> - interrupts = <1 2 3>;
> - reg = <0x0 0x2010000 0x0 0x1000>;
> - next-level-cache = <&L25 &L40 &L36>;
> - memory-region = <&l2_lim>;
> - };
> diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> new file mode 100644
> index 0000000..e14c8c6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
> @@ -0,0 +1,92 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (C) 2020 SiFive, Inc.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SiFive L2 Cache Controller
> +
> +maintainers:
> + - Sagar Kadam <sagar.kadam@...ive.com>
> + - Yash Shah <yash.shah@...ive.com>
> + - Paul Walmsley <paul.walmsley@...ive.com>
> +
> +description:
> + The SiFive Level 2 Cache Controller is used to provide access to fast copies
> + of memory for masters in a Core Complex. The Level 2 Cache Controller also
> + acts as directory-based coherency manager.
> + All the properties in ePAPR/DeviceTree specification applies for this platform.
> +
> +allOf:
> + - $ref: /schemas/cache-controller.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - sifive,fu540-c000-ccache
> + description: |
> + Should have "sifive,<soc>-cache" and "cache".
That's not what the schema describes or the example has (the 'cache'
fallback).
> +
> + cache-block-size:
> + const: 64
> +
> + cache-level:
> + const: 2
> +
> + cache-sets:
> + const: 1024
> +
> + cache-size:
> + const: 2097152
> +
> + cache-unified: true
> +
> + interrupts:
> + description: |
> + Must contain entries for DirError, DataError and DataFail signals.
> + minItems: 1
The old doc said must have 3 entries.
> + maxItems: 3
> +
> + reg:
> + maxItems: 1
> + description: address of cache controller's registers.
Drop this.
> +
> +
One blank line please.
> + next-level-cache:
> + description: |
> + Phandle to the next level cache if present.
No need to re-describe common properties unless you have something
unique to this device to say. Just:
'next-level-cache: true'
> +
> + memory-region:
> + description: |
> + The reference to the reserved-memory for the L2 Loosely Integrated memory region.
> + The reserved memory node should be defined as per the bindings in reserved-memory.txt.
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - cache-block-size
> + - cache-level
> + - cache-sets
> + - cache-size
> + - cache-unified
> + - interrupts
> + - reg
> +
> +examples:
> + - |
> + cache-controller@...0000 {
> + compatible = "sifive,fu540-c000-ccache";
> + cache-block-size = <64>;
> + cache-level = <2>;
> + cache-sets = <1024>;
> + cache-size = <2097152>;
> + cache-unified;
> + reg = <0x2010000 0x1000>;
> + interrupt-parent = <&plic0>;
> + interrupts = <1 2 3>;
> + next-level-cache = <&L25>;
> + memory-region = <&l2_lim>;
> + };
> --
> 2.7.4
>
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