linux-kernel - [PATCH V5 04/17] arm64: dts: mt8183: add performance state support of scpsys

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Date:   Mon, 14 Sep 2020 11:04:31 +0800
From:   Henry Chen <henryc.chen@...iatek.com>
To:     Georgi Djakov <georgi.djakov@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Viresh Kumar <vireshk@...nel.org>,
        Stephen Boyd <swboyd@...omium.org>,
        Ryan Case <ryandcase@...omium.org>,
        Mark Brown <broonie@...nel.org>
CC:     Mark Rutland <mark.rutland@....com>,
        Nicolas Boichat <drinkcat@...gle.com>,
        Fan Chen <fan.chen@...iatek.com>,
        James Liao <jamesjj.liao@...iatek.com>,
        Arvin Wang <arvin.wang@...iatek.com>,
        Mike Turquette <mturquette@...aro.org>,
        <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <linux-pm@...r.kernel.org>,
        Henry Chen <henryc.chen@...iatek.com>
Subject: [PATCH V5 04/17] arm64: dts: mt8183: add performance state support of scpsys

Add support for performance state of scpsys on mt8183 platform

Signed-off-by: Henry Chen <henryc.chen@...iatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index d85bae7..82ca929 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -12,6 +12,7 @@
 #include <dt-bindings/reset-controller/mt8183-resets.h>
 #include <dt-bindings/phy/phy.h>
 #include "mt8183-pinfunc.h"
+#include <dt-bindings/soc/mtk,dvfsrc.h>
 
 / {
 	compatible = "mediatek,mt8183";
@@ -340,6 +341,27 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
+			operating-points-v2 = <&dvfsrc_opp_table>;
+			dvfsrc_opp_table: opp-table {
+				compatible = "operating-points-v2-level";
+
+				dvfsrc_vol_min: opp1 {
+					opp,level = <MT8183_DVFSRC_LEVEL_1>;
+				};
+
+				dvfsrc_freq_medium: opp2 {
+					opp,level = <MT8183_DVFSRC_LEVEL_2>;
+				};
+
+				dvfsrc_freq_max: opp3 {
+					opp,level = <MT8183_DVFSRC_LEVEL_3>;
+				};
+
+				dvfsrc_vol_max: opp4 {
+					opp,level = <MT8183_DVFSRC_LEVEL_4>;
+				};
+			};
+
 			audio@...183_POWER_DOMAIN_AUDIO {
 				reg = <MT8183_POWER_DOMAIN_AUDIO>;
 			};
-- 
1.9.1