[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-Id: <20200914160500.21356-1-tsbogend@alpha.franken.de>
Date: Mon, 14 Sep 2020 18:05:00 +0200
From: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
To: Florian Fainelli <florian@...nwrt.org>, linux-mips@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH] MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.
Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@...ha.franken.de>
---
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c95fa3a2484c..8f328298f8cc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -877,6 +877,7 @@ config SNI_RM
select I8253
select I8259
select ISA
+ select MIPS_L1_CACHE_SHIFT_6
select SWAP_IO_SPACE if CPU_BIG_ENDIAN
select SYS_HAS_CPU_R4X00
select SYS_HAS_CPU_R5000
--
2.16.4
Powered by blists - more mailing lists