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Date:   Mon, 14 Sep 2020 19:30:39 -0600
From:   Rob Herring <robh@...nel.org>
To:     Zhiqiang Hou <Zhiqiang.Hou@....com>
Cc:     bhelgaas@...gle.com, linux-kernel@...r.kernel.org,
        shawnguo@...nel.org, leoyang.li@....com, linux-pci@...r.kernel.org,
        minghuan.Lian@....com, robh+dt@...nel.org,
        gustavo.pimentel@...opsys.com, lorenzo.pieralisi@....com,
        roy.zang@....com, mingkai.hu@....com, devicetree@...r.kernel.org
Subject: Re: [PATCH 3/7] dt-bindings: pci: layerscape-pci: Add a optional
 property big-endian

On Mon, 07 Sep 2020 13:37:57 +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@....com>
> 
> This property is to indicate the endianness when accessing the
> PEX_LUT and PF register block, so if these registers are
> implemented in big-endian, specify this property.
> 
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
> ---
>  Documentation/devicetree/bindings/pci/layerscape-pci.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Acked-by: Rob Herring <robh@...nel.org>

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