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Message-ID: <5e1510f4-b0c4-2cff-b3f8-b6715d228149@gmail.com>
Date: Wed, 16 Sep 2020 14:19:27 +0200
From: Matthias Brugger <matthias.bgg@...il.com>
To: Enric Balletbo i Serra <enric.balletbo@...labora.com>,
linux-kernel@...r.kernel.org
Cc: Collabora Kernel ML <kernel@...labora.com>, fparent@...libre.com,
drinkcat@...omium.org, hsinyi@...omium.org, weiyi.lu@...iatek.com,
Matthias Brugger <mbrugger@...e.com>,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH 11/12] soc: mediatek: pm-domains: Add support for mt8183
On 16/09/2020 11:46, Matthias Brugger wrote:
>
>
> On 10/09/2020 19:28, Enric Balletbo i Serra wrote:
>> From: Matthias Brugger <mbrugger@...e.com>
>>
>> Add the needed board data to support mt8183 SoC.
>>
>> Signed-off-by: Matthias Brugger <mbrugger@...e.com>
>> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
>> ---
>>
>> drivers/soc/mediatek/mtk-pm-domains.c | 162 ++++++++++++++++++++++++++
>> include/linux/soc/mediatek/infracfg.h | 28 +++++
>> 2 files changed, 190 insertions(+)
>>
>> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c
>> b/drivers/soc/mediatek/mtk-pm-domains.c
>> index 29e88adc8ea6..aa434f616fee 100644
>> --- a/drivers/soc/mediatek/mtk-pm-domains.c
>> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> [...]
>> +/*
>> + * MT8183 power domain support
>> + */
>> +static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
>> + [MT8183_POWER_DOMAIN_AUDIO] = {
>> + .sta_mask = PWR_STATUS_AUDIO,
>> + .ctl_offs = 0x0314,
>> + .sram_pdn_bits = GENMASK(11, 8),
>> + .sram_pdn_ack_bits = GENMASK(15, 12),
>> + },
>> + [MT8183_POWER_DOMAIN_CONN] = {
>> + .sta_mask = PWR_STATUS_CONN,
>> + .ctl_offs = 0x032c,
>> + .sram_pdn_bits = 0,
>> + .sram_pdn_ack_bits = 0,
>> + .bp_infracfg = {
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, 0x2a0, 0x2a4, 0x228),
>
> We have repeating values triplets for set, clear and status register in infracfg
> and SMI.
>
> Weiyi can you help to get names to this registers? I wasn't able to find
> anything in the datasheet.
I think for the infracfg part I figured it out:
#define INFRA_TOPAXI_PROTECTEN_SET 0x2a0
#define INFRA_TOPAXI_PROTECTEN_CLR 0x2a4
#define INFRA_TOPAXI_PROTECTEN_STA1 0x228
#define INFRA_TOPAXI_PROTECTEN_1_SET 0x2a8
#define INFRA_TOPAXI_PROTECTEN_1_CLR 0x2ac
#define INFRA_TOPAXI_PROTECTEN_STA1_1 0x258
#define INFRA_TOPAXI_PROTECTEN_MCU_SET 0x2d4
#define INFRA_TOPAXI_PROTECTEN_MCU_CLR 0x2d8
#define INFRA_TOPAXI_PROTECTEN_MM_STA1 0x2ec
Weiyi, can you still provide the register names for the SMI?
Thanks in advance!
Matthias
>
> Thanks!
> Matthias
>
>> + },
>> + },
>> + [MT8183_POWER_DOMAIN_MFG_ASYNC] = {
>> + .sta_mask = PWR_STATUS_MFG_ASYNC,
>> + .ctl_offs = 0x0334,
>> + .sram_pdn_bits = 0,
>> + .sram_pdn_ack_bits = 0,
>> + },
>> + [MT8183_POWER_DOMAIN_MFG] = {
>> + .sta_mask = PWR_STATUS_MFG,
>> + .ctl_offs = 0x0338,
>> + .sram_pdn_bits = GENMASK(8, 8),
>> + .sram_pdn_ack_bits = GENMASK(12, 12),
>> + },
>> + [MT8183_POWER_DOMAIN_MFG_CORE0] = {
>> + .sta_mask = BIT(7),
>> + .ctl_offs = 0x034c,
>> + .sram_pdn_bits = GENMASK(8, 8),
>> + .sram_pdn_ack_bits = GENMASK(12, 12),
>> + },
>> + [MT8183_POWER_DOMAIN_MFG_CORE1] = {
>> + .sta_mask = BIT(20),
>> + .ctl_offs = 0x0310,
>> + .sram_pdn_bits = GENMASK(8, 8),
>> + .sram_pdn_ack_bits = GENMASK(12, 12),
>> + },
>> + [MT8183_POWER_DOMAIN_MFG_2D] = {
>> + .sta_mask = PWR_STATUS_MFG_2D,
>> + .ctl_offs = 0x0348,
>> + .sram_pdn_bits = GENMASK(8, 8),
>> + .sram_pdn_ack_bits = GENMASK(12, 12),
>> + .bp_infracfg = {
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, 0x2a8, 0x2ac, 0x258),
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, 0x2a0, 0x2a4, 0x228),
>> + },
>> + },
>> + [MT8183_POWER_DOMAIN_DISP] = {
>> + .sta_mask = PWR_STATUS_DISP,
>> + .ctl_offs = 0x030c,
>> + .sram_pdn_bits = GENMASK(8, 8),
>> + .sram_pdn_ack_bits = GENMASK(12, 12),
>> + .bp_infracfg = {
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, 0x2a8, 0x2ac, 0x258),
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, 0x2a0, 0x2a4, 0x228),
>> + },
>> + .bp_smi = {
>> + BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP, 0x3c4, 0x3c8, 0x3c0),
>> + },
>> + },
>> + [MT8183_POWER_DOMAIN_CAM] = {
>> + .sta_mask = BIT(25),
>> + .ctl_offs = 0x0344,
>> + .sram_pdn_bits = GENMASK(9, 8),
>> + .sram_pdn_ack_bits = GENMASK(13, 12),
>> + .bp_infracfg = {
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, 0x2d4, 0x2d8, 0x2ec),
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, 0x2a0, 0x2a4, 0x228),
>> + BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, 0x2d4, 0x2d8,
>> 0x2ec),
>> + },
>> + .bp_smi = {
>> + BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM, 0x3c4, 0x3c8, 0x3c0),
>> + },
>> + },
>> + [MT8183_POWER_DOMAIN_ISP] = {
>> + .sta_mask = PWR_STATUS_ISP,
>> + .ctl_offs = 0x0308,
>> + .sram_pdn_bits = GENMASK(9, 8),
>> + .sram_pdn_ack_bits = GENMASK(13, 12),
>> + .bp_infracfg = {
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP, 0x2d4, 0x2d8, 0x2ec),
>> + BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, 0x2d4, 0x2d8,
>> 0x2ec),
>> + },
>> + .bp_smi = {
>> + BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP, 0x3c4, 0x3c8, 0x3c0),
>> + },
>> + },
>> + [MT8183_POWER_DOMAIN_VDEC] = {
>> + .sta_mask = BIT(31),
>> + .ctl_offs = 0x0300,
>> + .sram_pdn_bits = GENMASK(8, 8),
>> + .sram_pdn_ack_bits = GENMASK(12, 12),
>> + .bp_smi = {
>> + BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC, 0x3c4, 0x3c8, 0x3c0),
>> + },
>> + },
>> + [MT8183_POWER_DOMAIN_VENC] = {
>> + .sta_mask = PWR_STATUS_VENC,
>> + .ctl_offs = 0x0304,
>> + .sram_pdn_bits = GENMASK(11, 8),
>> + .sram_pdn_ack_bits = GENMASK(15, 12),
>> + .bp_smi = {
>> + BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC, 0x3c4, 0x3c8, 0x3c0),
>> + },
>> + },
>> + [MT8183_POWER_DOMAIN_VPU_TOP] = {
>> + .sta_mask = BIT(26),
>> + .ctl_offs = 0x0324,
>> + .sram_pdn_bits = GENMASK(8, 8),
>> + .sram_pdn_ack_bits = GENMASK(12, 12),
>> + .bp_infracfg = {
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, 0x2d4, 0x2d8, 0x2ec),
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP, 0x2a0, 0x2a4, 0x228),
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, 0x2d4, 0x2d8,
>> 0x2ec),
>> + },
>> + .bp_smi = {
>> + BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, 0x3c4, 0x3c8,
>> 0x3c0),
>> + },
>> + },
>> + [MT8183_POWER_DOMAIN_VPU_CORE0] = {
>> + .sta_mask = BIT(27),
>> + .ctl_offs = 0x33c,
>> + .sram_pdn_bits = GENMASK(11, 8),
>> + .sram_pdn_ack_bits = GENMASK(13, 12),
>> + .bp_infracfg = {
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, 0x2c4, 0x2c8,
>> 0x2e4),
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, 0x2c4,
>> 0x2c8, 0x2e4),
>> + },
>> + .caps = MTK_SCPD_SRAM_ISO,
>> + },
>> + [MT8183_POWER_DOMAIN_VPU_CORE1] = {
>> + .sta_mask = BIT(28),
>> + .ctl_offs = 0x0340,
>> + .sram_pdn_bits = GENMASK(11, 8),
>> + .sram_pdn_ack_bits = GENMASK(13, 12),
>> + .bp_infracfg = {
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, 0x2c4, 0x2c8,
>> 0x2e4),
>> + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, 0x2c4,
>> 0x2c8, 0x2e4),
>> + },
>> + .caps = MTK_SCPD_SRAM_ISO,
>> + },
>> +};
>> +
>> static const struct scpsys_soc_data mt8173_scpsys_data = {
>> .domains = scpsys_domain_data_mt8173,
>> .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173),
>> @@ -705,11 +856,22 @@ static const struct scpsys_soc_data mt8173_scpsys_data = {
>> .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
>> };
>> +static const struct scpsys_soc_data mt8183_scpsys_data = {
>> + .domains = scpsys_domain_data_mt8183,
>> + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183),
>> + .pwr_sta_offs = 0x0180,
>> + .pwr_sta2nd_offs = 0x0184
>> +};
>> +
>> static const struct of_device_id scpsys_of_match[] = {
>> {
>> .compatible = "mediatek,mt8173-power-controller",
>> .data = &mt8173_scpsys_data,
>> },
>> + {
>> + .compatible = "mediatek,mt8183-power-controller",
>> + .data = &mt8183_scpsys_data,
>> + },
>> { }
>> };
>> diff --git a/include/linux/soc/mediatek/infracfg.h
>> b/include/linux/soc/mediatek/infracfg.h
>> index 3f18cddffb44..2913ede9d734 100644
>> --- a/include/linux/soc/mediatek/infracfg.h
>> +++ b/include/linux/soc/mediatek/infracfg.h
>> @@ -2,6 +2,34 @@
>> #ifndef __SOC_MEDIATEK_INFRACFG_H
>> #define __SOC_MEDIATEK_INFRACFG_H
>> +#define MT8183_TOP_AXI_PROT_EN_DISP (BIT(10) | BIT(11))
>> +#define MT8183_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(14))
>> +#define MT8183_TOP_AXI_PROT_EN_MFG (BIT(21) | BIT(22))
>> +#define MT8183_TOP_AXI_PROT_EN_CAM BIT(28)
>> +#define MT8183_TOP_AXI_PROT_EN_VPU_TOP BIT(27)
>> +#define MT8183_TOP_AXI_PROT_EN_1_DISP (BIT(16) | BIT(17))
>> +#define MT8183_TOP_AXI_PROT_EN_1_MFG GENMASK(21, 19)
>> +#define MT8183_TOP_AXI_PROT_EN_MM_ISP (BIT(3) | BIT(8))
>> +#define MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND BIT(10)
>> +#define MT8183_TOP_AXI_PROT_EN_MM_CAM (BIT(4) | BIT(5) | \
>> + BIT(9) | BIT(13))
>> +#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP (GENMASK(9, 6) | \
>> + BIT(12))
>> +#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND (BIT(10) | BIT(11))
>> +#define MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(11)
>> +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND (BIT(0) | BIT(2) | \
>> + BIT(4))
>> +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND (BIT(1) | BIT(3) | \
>> + BIT(5))
>> +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0 BIT(6)
>> +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1 BIT(7)
>> +#define MT8183_SMI_COMMON_SMI_CLAMP_DISP GENMASK(7, 0)
>> +#define MT8183_SMI_COMMON_SMI_CLAMP_VENC BIT(1)
>> +#define MT8183_SMI_COMMON_SMI_CLAMP_ISP BIT(2)
>> +#define MT8183_SMI_COMMON_SMI_CLAMP_CAM (BIT(3) | BIT(4))
>> +#define MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP (BIT(5) | BIT(6))
>> +#define MT8183_SMI_COMMON_SMI_CLAMP_VDEC BIT(7)
>> +
>> #define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
>> #define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
>> #define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
>>
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