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Message-Id: <20200916030311.17280-1-qiang.zhao@nxp.com>
Date: Wed, 16 Sep 2020 11:03:10 +0800
From: Qiang Zhao <qiang.zhao@....com>
To: shawnguo@...nel.org, robh+dt@...nel.org, mturquette@...libre.com
Cc: andy.tang@....com, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
Zhao Qiang <qiang.zhao@....com>
Subject: [PATCH 1/2] clk: qoriq: modify MAX_PLL_DIV to 32
From: Zhao Qiang <qiang.zhao@....com>
On LS2088A, Watchdog need clk divided by 32,
so modify MAX_PLL_DIV to 32
Signed-off-by: Zhao Qiang <qiang.zhao@....com>
---
drivers/clk/clk-qoriq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 5942e98..46101c6 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -31,7 +31,7 @@
#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
#define CGB_PLL1 4
#define CGB_PLL2 5
-#define MAX_PLL_DIV 16
+#define MAX_PLL_DIV 32
struct clockgen_pll_div {
struct clk *clk;
--
2.7.4
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