lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <ff371bf2-f030-f28e-f467-c3bcca5b33df@baylibre.com>
Date:   Wed, 16 Sep 2020 09:11:11 +0200
From:   Neil Armstrong <narmstrong@...libre.com>
To:     Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc:     khilman@...libre.com, balbi@...nel.org,
        linux-amlogic@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-usb@...r.kernel.org
Subject: Re: [PATCH 3/5] usb: dwc-meson-g12a: Add support for USB on AXG SoCs

On 15/09/2020 21:59, Martin Blumenstingl wrote:
> Hi Neil,
> 
> On Wed, Sep 9, 2020 at 6:04 PM Neil Armstrong <narmstrong@...libre.com> wrote:
>>
>> The Amlogic AXG is close from the GXL Glue but with a single OTG PHY.
> s/close from/close to/
> 
> [...]
>> +static struct dwc3_meson_g12a_drvdata axg_drvdata = {
>> +       .otg_switch_supported = true,
>> +       .clks = meson_gxl_clocks,
>> +       .num_clks = ARRAY_SIZE(meson_gxl_clocks),
>> +       .phy_names = meson_a1_phy_names,
>> +       .num_phys = ARRAY_SIZE(meson_a1_phy_names),
> I wonder if we should also update the comment for meson_a1_phy_names
> to understand that part I had to go back to the dt-bindings patch
Sure,

Thanks,
Neil

> 
> 
> Best regards,
> Martin
> 

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ