lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <20200916121538.GJ2968@vkoul-mobl>
Date:   Wed, 16 Sep 2020 17:45:38 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@...el.com>
Cc:     kishon@...com, robh+dt@...nel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, andriy.shevchenko@...ux.intel.com,
        vadivel.muruganx.ramuthevar@...ux.intel.com,
        eswara.kota@...ux.intel.com, lakshmi.bai.raja.subramanian@...el.com
Subject: Re: [PATCH v9 0/3] phy: intel: Add Keem Bay eMMC PHY support

On 14-09-20, 07:55, Wan Ahmad Zainie wrote:
> Hi.
> 
> The first patch is added to rename rename
> phy-intel-{combo,emmc}.c to phy-intel-lgm-{combo,emmc}.c.
> 
> The second patch is to document DT bindings for Keem Bay eMMC PHY.
> 
> The the third is the driver file, loosely based on phy-rockchip-emmc.c
> and phy-intel-emmc.c. The latter is not being reused as there are
> quite a number of differences i.e. registers offset, supported clock
> rates, bitfield to set.
> 
> The patch was tested with Keem Bay evaluation module board.

Applied all, thanks

-- 
~Vinod

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ