linux-kernel - [PATCH 0/2] Repair X1000E SoC L2 cache capacity detection.

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Message-Id: <20200919124437.89576-1-zhouyanjie@wanyeetech.com>
Date:   Sat, 19 Sep 2020 20:44:35 +0800
From:   周琰杰 (Zhou Yanjie) 
        <zhouyanjie@...yeetech.com>
To:     paulburton@...nel.org, tsbogend@...ha.franken.de,
        paul@...pouillou.net
Cc:     linux-kernel@...r.kernel.org, linux-mips@...r.kernel.org,
        jiaxun.yang@...goat.com, rppt@...nel.org,
        Sergey.Semin@...kalelectronics.ru,
        Alexey.Malahov@...kalelectronics.ru, akpm@...ux-foundation.org,
        dongsheng.qiu@...enic.com, aric.pzqi@...enic.com,
        rick.tyliu@...enic.com, yanfei.li@...enic.com,
        sernia.zhou@...mail.com, zhenwenjin@...il.com
Subject: [PATCH 0/2] Repair X1000E SoC L2 cache capacity detection.

The X1000E SoC has a 4-way L2 cache with a capacity of 128 KiB.
The current code cannot detect its correctly, which will cause
the CU1000-Neo board using the X1000E SoC to report that it
has found a 5-way 320KiB L2 cache at boot time. This series
of patches is to fix this problem.

周琰杰 (Zhou Yanjie) (2):
  MIPS: X1000E: Add X1000E system type.
  MIPS: Ingenic: Fix bugs when detecting X1000E's L2 cache.

 arch/mips/generic/board-ingenic.c | 3 +++
 arch/mips/include/asm/bootinfo.h  | 1 +
 arch/mips/mm/sc-mips.c            | 1 +
 3 files changed, 5 insertions(+)

-- 
2.11.0