linux-kernel - [PATCH 2/2] MIPS: Ingenic: Fix bugs when detecting X1000E's L2 cache.

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Message-Id: <20200919124437.89576-3-zhouyanjie@wanyeetech.com>
Date:   Sat, 19 Sep 2020 20:44:37 +0800
From:   周琰杰 (Zhou Yanjie) 
        <zhouyanjie@...yeetech.com>
To:     paulburton@...nel.org, tsbogend@...ha.franken.de,
        paul@...pouillou.net
Cc:     linux-kernel@...r.kernel.org, linux-mips@...r.kernel.org,
        jiaxun.yang@...goat.com, rppt@...nel.org,
        Sergey.Semin@...kalelectronics.ru,
        Alexey.Malahov@...kalelectronics.ru, akpm@...ux-foundation.org,
        dongsheng.qiu@...enic.com, aric.pzqi@...enic.com,
        rick.tyliu@...enic.com, yanfei.li@...enic.com,
        sernia.zhou@...mail.com, zhenwenjin@...il.com
Subject: [PATCH 2/2] MIPS: Ingenic: Fix bugs when detecting X1000E's L2 cache.

Fix bugs when detecting L2 cache sets value and ways value.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@...yeetech.com>
---
 arch/mips/mm/sc-mips.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 97dc0511e63f..145b39ecb246 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -235,6 +235,7 @@ static inline int __init mips_sc_probe(void)
 		 * According to config2 it would be 5-ways and 512-sets,
 		 * but that is contradicted by all documentation.
 		 */
+		case MACH_INGENIC_X1000E:
 		case MACH_INGENIC_X1000:
 			c->scache.sets = 256;
 			c->scache.ways = 4;
-- 
2.11.0