linux-kernel - Repair Ingenic SoCs L2 cache capacity detection.

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Message-Id: <20200921174522.33866-1-zhouyanjie@wanyeetech.com>
Date:   Tue, 22 Sep 2020 01:45:20 +0800
From:   周琰杰 (Zhou Yanjie) 
        <zhouyanjie@...yeetech.com>
To:     tsbogend@...ha.franken.de, paul@...pouillou.net,
        paulburton@...nel.org
Cc:     linux-kernel@...r.kernel.org, linux-mips@...r.kernel.org,
        jiaxun.yang@...goat.com, Sergey.Semin@...kalelectronics.ru,
        akpm@...ux-foundation.org, rppt@...nel.org,
        dongsheng.qiu@...enic.com, aric.pzqi@...enic.com,
        rick.tyliu@...enic.com, yanfei.li@...enic.com,
        sernia.zhou@...mail.com, zhenwenjin@...il.com
Subject: Repair Ingenic SoCs L2 cache capacity detection.

1.The X1000E SoC has a 4-way L2 cache with a capacity of 128 KiB.
  The current code cannot detect its correctly, which will cause the
  CU1000-Neo board using the X1000E SoC to report that it has found
  a 5-way 320KiB L2 cache at boot time.
2.The JZ4775 SoC has a 4-way L2 cache with a capacity of 256 KiB.
  The current code cannot detect its correctly, which will cause the
  Mensa board using the JZ4775 SoC to report that it has found a 5-way
  320KiB L2 cache at boot time.

This series of patches is to fix this problem.

周琰杰 (Zhou Yanjie) (2):
  MIPS: Ingenic: Add system type for new Ingenic SoCs.
  MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.

 arch/mips/generic/board-ingenic.c | 12 ++++++++++++
 arch/mips/include/asm/bootinfo.h  |  2 ++
 arch/mips/mm/sc-mips.c            |  2 ++
 3 files changed, 16 insertions(+)

-- 
2.11.0