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Message-ID: <CAHp75Vd2uz-QrEFshUr=e719VBX2zYzvOhVC07BpHfvi0WDgOA@mail.gmail.com>
Date:   Mon, 21 Sep 2020 10:55:49 +0300
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Ed Wildgoose <lists@...dgooses.com>,
        Hans de Goede <hdegoede@...hat.com>,
        Mark Gross <mgross@...ux.intel.com>
Cc:     Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Florian Eckert <fe@....tdt.de>,
        "Enrico Weigelt, metux IT consult" <info@...ux.net>,
        Darren Hart <dvhart@...radead.org>,
        Andy Shevchenko <andy@...radead.org>,
        Platform Driver <platform-driver-x86@...r.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>
Subject: Re: [PATCH] gpio: gpio-amd-fch: Fix typo on define of AMD_FCH_GPIO_REG_GPIO55_DEVSLP0

On Sun, Sep 20, 2020 at 11:33 PM Ed Wildgoose <lists@...dgooses.com> wrote:
>
> Schematics show that the GPIO number is 55 (not 59). Trivial typo.

Does it still DEVSLP0? Perhaps you need to drop that part as well.

...

>  #define APU2_GPIO_REG_LED3             AMD_FCH_GPIO_REG_GPIO59_DEVSLP1
>  #define APU2_GPIO_REG_MODESW           AMD_FCH_GPIO_REG_GPIO32_GE1
>  #define APU2_GPIO_REG_SIMSWAP          AMD_FCH_GPIO_REG_GPIO33_GE2
> -#define APU2_GPIO_REG_MPCIE2           AMD_FCH_GPIO_REG_GPIO59_DEVSLP0
> +#define APU2_GPIO_REG_MPCIE2           AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
>  #define APU2_GPIO_REG_MPCIE3           AMD_FCH_GPIO_REG_GPIO51
>
>  /* Order in which the GPIO lines are defined in the register list */
> diff --git a/include/linux/platform_data/gpio/gpio-amd-fch.h b/include/linux/platform_data/gpio/gpio-amd-fch.h
> index 9e46678ed..255d51c9d 100644
> --- a/include/linux/platform_data/gpio/gpio-amd-fch.h
> +++ b/include/linux/platform_data/gpio/gpio-amd-fch.h
> @@ -19,7 +19,7 @@
>  #define AMD_FCH_GPIO_REG_GPIO49                0x40
>  #define AMD_FCH_GPIO_REG_GPIO50                0x41
>  #define AMD_FCH_GPIO_REG_GPIO51                0x42
> -#define AMD_FCH_GPIO_REG_GPIO59_DEVSLP0        0x43
> +#define AMD_FCH_GPIO_REG_GPIO55_DEVSLP0        0x43
>  #define AMD_FCH_GPIO_REG_GPIO57                0x44
>  #define AMD_FCH_GPIO_REG_GPIO58                0x45
>  #define AMD_FCH_GPIO_REG_GPIO59_DEVSLP1        0x46


-- 
With Best Regards,
Andy Shevchenko

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