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Message-Id: <20200924084618.12442-1-pali@kernel.org>
Date:   Thu, 24 Sep 2020 10:46:18 +0200
From:   Pali Rohár <pali@...nel.org>
To:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Rob Herring <robh@...nel.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>
Cc:     linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH] PCI: aardvark: Update comment about disabling link training

It is not HW bug or workaround for some cards but it is requirement by PCI
Express spec. After fundamental reset is needed 100ms delay prior enabling
link training. So update comment in code to reflect this requirement.

Signed-off-by: Pali Rohár <pali@...nel.org>
---
 drivers/pci/controller/pci-aardvark.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 50ab6d7519ae..19b9b79226e5 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -259,7 +259,12 @@ static void advk_pcie_issue_perst(struct advk_pcie *pcie)
 	if (!pcie->reset_gpio)
 		return;
 
-	/* PERST does not work for some cards when link training is enabled */
+	/*
+	 * As required by PCI Express spec a delay for at least 100ms after
+	 * de-asserting PERST# signal is needed before link training is enabled.
+	 * So ensure that link training is disabled prior de-asserting PERST#
+	 * signal to fulfill that PCI Express spec requirement.
+	 */
 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
 	reg &= ~LINK_TRAINING_EN;
 	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
-- 
2.20.1

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