linux-kernel - Re: [PATCH v2 0/5] PCI: dwc: improve msi handling

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Date:   Fri, 25 Sep 2020 09:53:45 +0100
From:   Jon Hunter <jonathanh@...dia.com>
To:     Jisheng Zhang <Jisheng.Zhang@...aptics.com>,
        Kishon Vijay Abraham I <kishon@...com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Rob Herring <robh@...nel.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Jingoo Han <jingoohan1@...il.com>,
        Kukjin Kim <kgene@...nel.org>,
        Krzysztof Kozlowski <krzk@...nel.org>,
        Richard Zhu <hongxing.zhu@....com>,
        Lucas Stach <l.stach@...gutronix.de>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Fabio Estevam <festevam@...il.com>,
        NXP Linux Team <linux-imx@....com>,
        "Yue Wang" <yue.wang@...ogic.com>,
        Kevin Hilman <khilman@...libre.com>,
        "Neil Armstrong" <narmstrong@...libre.com>,
        Jerome Brunet <jbrunet@...libre.com>,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        Jesper Nilsson <jesper.nilsson@...s.com>,
        Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
        Xiaowei Song <songxiaowei@...ilicon.com>,
        Binghui Wang <wangbinghui@...ilicon.com>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Stanimir Varbanov <svarbanov@...sol.com>,
        Pratyush Anand <pratyush.anand@...il.com>,
        Thierry Reding <thierry.reding@...il.com>,
        Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>,
        Masahiro Yamada <yamada.masahiro@...ionext.com>
CC:     <linux-omap@...r.kernel.org>, <linux-pci@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-samsung-soc@...r.kernel.org>,
        <linux-amlogic@...ts.infradead.org>, <linux-arm-kernel@...s.com>,
        <linux-arm-msm@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
        Vidya Sagar <vidyas@...dia.com>
Subject: Re: [PATCH v2 0/5] PCI: dwc: improve msi handling


On 24/09/2020 12:05, Jisheng Zhang wrote:
> Improve the msi code:
> 1. Add proper error handling.
> 2. Move dw_pcie_msi_init() from each users to designware host to solve
> msi page leakage in resume path.

Apologies if this is slightly off topic, but I have been meaning to ask
about MSIs and PCI. On Tegra194 which uses the DWC PCI driver, whenever we
hotplug CPUs we see the following warnings ...

 [      79.068351] WARNING KERN IRQ70: set affinity failed(-22).
 [      79.068362] WARNING KERN IRQ71: set affinity failed(-22).

These interrupts are the MSIs ...

70:          0          0          0          0          0          0          0          0   PCI-MSI 134217728 Edge      PCIe PME, aerdrv
71:          0          0          0          0          0          0          0          0   PCI-MSI 134742016 Edge      ahci[0001:01:00.0]

This caused because ...

 static int dw_pci_msi_set_affinity(struct irq_data *d,
                                    const struct cpumask *mask, bool force)
 {
         return -EINVAL;
 }

Now the above is not unique to the DWC PCI host driver, it appears that
most PCIe drivers also do the same. However, I am curious if there is
any way to avoid the above warnings given that setting the affinity does
not appear to be supported in anyway AFAICT.

Cheers
Jon 

-- 
nvpublic