linux-kernel - Re: [PATCH v2 0/5] PCI: dwc: improve msi handling

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Date:   Fri, 25 Sep 2020 17:27:24 +0800
From:   Jisheng Zhang <Jisheng.Zhang@...aptics.com>
To:     Jon Hunter <jonathanh@...dia.com>
Cc:     Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>,
        Neil Armstrong <narmstrong@...libre.com>,
        linux-pci@...r.kernel.org,
        Binghui Wang <wangbinghui@...ilicon.com>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Masahiro Yamada <yamada.masahiro@...ionext.com>,
        Thierry Reding <thierry.reding@...il.com>,
        linux-arm-kernel@...s.com, Vidya Sagar <vidyas@...dia.com>,
        Fabio Estevam <festevam@...il.com>,
        Jerome Brunet <jbrunet@...libre.com>,
        Rob Herring <robh@...nel.org>,
        Jesper Nilsson <jesper.nilsson@...s.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Kevin Hilman <khilman@...libre.com>,
        Pratyush Anand <pratyush.anand@...il.com>,
        linux-tegra@...r.kernel.org, Krzysztof Kozlowski <krzk@...nel.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Kukjin Kim <kgene@...nel.org>,
        NXP Linux Team <linux-imx@....com>,
        Xiaowei Song <songxiaowei@...ilicon.com>,
        Richard Zhu <hongxing.zhu@....com>,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        linux-arm-msm@...r.kernel.org,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Yue Wang <yue.wang@...ogic.com>,
        linux-samsung-soc@...r.kernel.org,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        linux-amlogic@...ts.infradead.org, linux-omap@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        Jingoo Han <jingoohan1@...il.com>,
        Andy Gross <agross@...nel.org>, linux-kernel@...r.kernel.org,
        Stanimir Varbanov <svarbanov@...sol.com>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
        Shawn Guo <shawnguo@...nel.org>,
        Lucas Stach <l.stach@...gutronix.de>
Subject: Re: [PATCH v2 0/5] PCI: dwc: improve msi handling

On Fri, 25 Sep 2020 17:17:12 +0800
Jisheng Zhang <Jisheng.Zhang@...aptics.com> wrote:

> CAUTION: Email originated externally, do not click links or open attachments unless you recognize the sender and know the content is safe.
> 
> 
> Hi Jon,
> 
> On Fri, 25 Sep 2020 09:53:45 +0100 Jon Hunter wrote:
> 
> 
> >
> > On 24/09/2020 12:05, Jisheng Zhang wrote:  
> > > Improve the msi code:
> > > 1. Add proper error handling.
> > > 2. Move dw_pcie_msi_init() from each users to designware host to solve
> > > msi page leakage in resume path.  
> >
> > Apologies if this is slightly off topic, but I have been meaning to ask
> > about MSIs and PCI. On Tegra194 which uses the DWC PCI driver, whenever we
> > hotplug CPUs we see the following warnings ...
> >
> >  [      79.068351] WARNING KERN IRQ70: set affinity failed(-22).
> >  [      79.068362] WARNING KERN IRQ71: set affinity failed(-22).
> >
> > These interrupts are the MSIs ...
> >
> > 70:          0          0          0          0          0          0          0          0   PCI-MSI 134217728 Edge      PCIe PME, aerdrv
> > 71:          0          0          0          0          0          0          0          0   PCI-MSI 134742016 Edge      ahci[0001:01:00.0]
> >
> > This caused because ...
> >
> >  static int dw_pci_msi_set_affinity(struct irq_data *d,
> >                                     const struct cpumask *mask, bool force)
> >  {
> >          return -EINVAL;
> >  }
> >
> > Now the above is not unique to the DWC PCI host driver, it appears that
> > most PCIe drivers also do the same. However, I am curious if there is
> > any way to avoid the above warnings given that setting the affinity does
> > not appear to be supported in anyway AFAICT.
> >  
> 
> 
> Could you please try below patch?
> 
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index bf25d783b5c5..7e5dc54d060e 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -197,7 +197,6 @@ static struct irq_chip dw_pci_msi_bottom_irq_chip = {
>         .name = "DWPCI-MSI",
>         .irq_ack = dw_pci_bottom_ack,
>         .irq_compose_msi_msg = dw_pci_setup_msi_msg,
> -       .irq_set_affinity = dw_pci_msi_set_affinity,
>         .irq_mask = dw_pci_bottom_mask,
>         .irq_unmask = dw_pci_bottom_unmask,
>  };

A complete patch w/o compiler warning:

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index bf25d783b5c5..18f719cfed0b 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -137,12 +137,6 @@ static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg)
 		(int)d->hwirq, msg->address_hi, msg->address_lo);
 }
 
-static int dw_pci_msi_set_affinity(struct irq_data *d,
-				   const struct cpumask *mask, bool force)
-{
-	return -EINVAL;
-}
-
 static void dw_pci_bottom_mask(struct irq_data *d)
 {
 	struct pcie_port *pp = irq_data_get_irq_chip_data(d);
@@ -197,7 +191,6 @@ static struct irq_chip dw_pci_msi_bottom_irq_chip = {
 	.name = "DWPCI-MSI",
 	.irq_ack = dw_pci_bottom_ack,
 	.irq_compose_msi_msg = dw_pci_setup_msi_msg,
-	.irq_set_affinity = dw_pci_msi_set_affinity,
 	.irq_mask = dw_pci_bottom_mask,
 	.irq_unmask = dw_pci_bottom_unmask,
 };